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git01.mediatek.com / filogic / atf / aef51b7a22038b35c87846e94dcac2618855a8ad / lib / extensions
  1. 34060b4 feat(cm): handle asymmetry for FEAT_TCR2 by Jayanth Dodderi Chidanand · Mon Sep 02 20:55:13 2024 +0100
  2. 9abe23b refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1 by Jayanth Dodderi Chidanand · Tue May 07 18:50:57 2024 +0100
  3. 58f89ed feat(trbe): introduce trbe_disable() function by Arvind Ram Prakash · Fri Jul 19 11:39:49 2024 -0500
  4. e01b422 feat(spe): introduce spe_disable() function by Manish Pandey · Thu Jul 18 16:17:45 2024 +0100
  5. 46dff39 chore(spe): rename spe_disable() to spe_stop() by Manish Pandey · Thu Jul 18 16:07:21 2024 +0100
  6. 62d87e7 feat(fgt2): add support for FEAT_FGT2 by Arvind Ram Prakash · Thu Jun 06 11:33:37 2024 -0500
  7. 05b4763 feat(debugv8p9): add support for FEAT_Debugv8p9 by Arvind Ram Prakash · Wed May 22 15:24:00 2024 -0500
  8. 118b335 feat(cm): context switch MDCR_EL3 register by Jayanth Dodderi Chidanand · Tue Jun 18 15:22:54 2024 +0100
  9. 9e505f9 refactor(cpufeat): add macro to simplify is_feat_xx_present by Sona Mathew · Wed Mar 13 11:33:54 2024 -0500
  10. 9275559 fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32 by Ahmad Fatoum · Tue Mar 12 18:36:46 2024 +0100
  11. fbbee6b refactor(cm): couple el2 registers with dependent feature flags by Jayanth Dodderi Chidanand · Wed Jan 24 20:05:07 2024 +0000
  12. 18d9379 fix(spe): invoke spe_disable during power domain off/suspend by Jayanth Dodderi Chidanand · Tue Jul 18 14:48:09 2023 +0100
  13. b5d9559 refactor(cm): move MPAM3_EL3 reg to per world context by Arvind Ram Prakash · Wed Nov 08 12:28:30 2023 -0600
  14. 4fc00d2 refactor(cm): move EL3 registers to global context by Elizabeth Ho · Tue Jul 18 14:10:25 2023 +0100
  15. ab28d4b fix(mpam): refine MPAM initialization and enablement process by Arvind Ram Prakash · Wed Oct 11 12:10:56 2023 -0500
  16. 8ae58f0 refactor(cm): clean up SCR_EL3 and CPTR_EL3 initialization by Boyan Karatotev · Thu Apr 20 11:00:50 2023 +0100
  17. eee28e7 chore: update to use Arm word across TF-A by Govindraj Raja · Tue Aug 01 15:52:40 2023 -0500
  18. 919d3c8 refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only by Boyan Karatotev · Mon Feb 13 16:32:47 2023 +0000
  19. 6e2fd8b fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly by Boyan Karatotev · Mon Feb 13 16:38:37 2023 +0000
  20. 1e966f3 refactor(amu): separate the EL2 and EL3 enablement code by Boyan Karatotev · Mon Mar 27 17:02:43 2023 +0100
  21. 6468d4a refactor(cpufeat): separate the EL2 and EL3 enablement code by Boyan Karatotev · Thu Feb 16 15:12:45 2023 +0000
  22. 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · Thu Feb 16 09:45:29 2023 +0000
  23. 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · Wed Feb 15 13:21:50 2023 +0000
  24. 9dd433f Merge changes from topic "bk/clearups" into integration by Olivier Deprez · Wed Jun 07 10:13:17 2023 +0200
  25. 7f5dcc7 refactor(cm): make SVE and SME build dependencies logical by Boyan Karatotev · Wed Mar 08 16:29:26 2023 +0000
  26. e7792e8 chore(pauth): remove redundant pauth_disable_el3() call by Boyan Karatotev · Mon Mar 06 14:45:15 2023 +0000
  27. cfe053a feat(sme): enable SME2 functionality for NS world by Jayanth Dodderi Chidanand · Tue Nov 08 10:31:07 2022 +0000
  28. d62c681 feat(cpufeat): enable FEAT_SVE for FEAT_STATE_CHECKED by Jayanth Dodderi Chidanand · Tue Mar 07 10:43:19 2023 +0000
  29. 605419a feat(cpufeat): enable FEAT_SME for FEAT_STATE_CHECKED by Jayanth Dodderi Chidanand · Mon Mar 06 23:56:14 2023 +0000
  30. 906776e refactor(amu): use new AMU feature check routines by Andre Przywara · Fri Mar 03 10:30:06 2023 +0000
  31. 0b7f1b0 refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1 by Andre Przywara · Tue Mar 21 13:53:19 2023 +0000
  32. 44e33e0 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  33. 84b8653 refactor(mpam): enable FEAT_MPAM for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  34. f3e8cfc refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  35. 06ea44e refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 17:30:43 2022 +0000
  36. c97c551 refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  37. 191eff6 refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED by Andre Przywara · Thu Nov 17 16:42:09 2022 +0000
  38. be028b4 fix(sme): add missing ISBs by Boyan Karatotev · Thu Oct 13 13:51:05 2022 +0100
  39. 6486997 feat(sve): support full SVE vector length by Mark Brown · Wed Apr 20 18:14:32 2022 +0100
  40. beaf5e8 feat(sme): fall back to SVE if SME is not there by Mark Brown · Mon May 09 13:26:36 2022 +0100
  41. a793ccc feat(trbe): add trbe under feature detection mechanism by Jayanth Dodderi Chidanand · Thu May 19 14:08:28 2022 +0100
  42. 6931675 feat(brbe): add brbe under feature detection mechanism by Jayanth Dodderi Chidanand · Mon May 09 12:33:03 2022 +0100
  43. 8a48954 Merge "fix(amu): limit virtual offset register access to NS world" into integration by Joanna Farley · Tue May 10 15:55:05 2022 +0200
  44. 8186596 feat(brbe): add BRBE support for NS world by johpow01 · Fri Jan 28 17:06:20 2022 -0600
  45. cc79927 fix(amu): limit virtual offset register access to NS world by John Powell · Tue Mar 29 00:25:59 2022 -0500
  46. 14dbc70 refactor(mpam): remove initialization of EL2 registers when EL2 is used by Zelalem Aweke · Wed Feb 02 15:29:13 2022 -0600
  47. 67fec3e feat(spe): add support for FEAT_SPEv1p2 by Manish V Badarkhe · Fri Dec 31 16:08:51 2021 +0000
  48. 9baade3 feat(sme): enable SME functionality by johpow01 · Thu Jul 08 14:14:00 2021 -0500
  49. e5dcf98 fix: libc: use long for 64-bit types on aarch64 by Scott Branden · Tue Aug 25 13:49:32 2020 -0700
  50. e9c3256 fix(amu): remove `amu_fconf.c` by Chris Kay · Mon Nov 01 11:11:45 2021 +0000
  51. 03be39d feat(mpmm): add support for MPMM by Chris Kay · Wed May 05 13:38:30 2021 +0100
  52. f11909f feat(amu): enable per-core AMU auxiliary counters by Chris Kay · Thu Aug 19 11:21:52 2021 +0100
  53. 26a7961 refactor(amu): refactor enablement and context switching by Chris Kay · Mon May 24 20:35:26 2021 +0100
  54. da81914 refactor(amu): detect auxiliary counters at runtime by Chris Kay · Tue May 25 15:24:18 2021 +0100
  55. a40141d refactor(amu): detect architected counters at runtime by Chris Kay · Tue May 25 12:33:18 2021 +0100
  56. 925fda4 refactor(amu): conditionally compile auxiliary counter support by Chris Kay · Tue May 25 10:42:56 2021 +0100
  57. a5fde28 refactor(amu): factor out register accesses by Chris Kay · Wed May 26 11:58:23 2021 +0100
  58. f13c6b5 refactor(amu)!: privatize unused AMU APIs by Chris Kay · Mon May 24 21:00:07 2021 +0100
  59. 1000ea8 build(amu): introduce `amu.mk` by Chris Kay · Wed May 19 19:24:37 2021 +0100
  60. 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · Thu Jul 08 09:33:18 2021 +0100
  61. f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · Tue Jun 29 11:44:20 2021 +0100
  62. 20df29c feat(trbe): enable access to trace buffer control registers from lower NS EL by Manish V Badarkhe · Fri Jul 02 09:10:56 2021 +0100
  63. cac7d16 fix(el3_runtime): fix SVE and AMU extension enablement flags by Arunachalam Ganapathy · Thu Jul 08 09:35:57 2021 +0100
  64. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
  65. ce59bd2 Merge "lib/extensions/ras: fix bug of binary search" into integration by Manish Pandey · Tue Mar 02 15:00:08 2021 +0100
  66. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · Fri Oct 02 13:41:11 2020 -0500
  67. bdbf627 lib/extensions/ras: fix bug of binary search by Heyi Guo · Wed Apr 22 20:00:00 2020 +0800
  68. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · Mon Nov 23 18:38:15 2020 +0000
  69. 7828f22 SPE: Fix feature detection by Andre Przywara · Fri Sep 11 09:18:09 2020 +0100
  70. a9c4521 TF-A AMU: remove AMU enable info print by Olivier Deprez · Thu Aug 13 12:55:54 2020 +0200
  71. 7e6306b TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · Tue Jul 14 08:17:56 2020 +0100
  72. 70f6597 Tegra194: add RAS exception handling by David Pu · Mon Mar 18 15:14:49 2019 -0700
  73. 1993355 TF-A: Fix wrong register read for MPAM extension by Alexei Fedorov · Tue May 26 13:16:41 2020 +0100
  74. 3dd9f2b TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U by Alexei Fedorov · Tue Oct 01 13:58:23 2019 +0100
  75. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  76. 72065ec Fix Coverity #342970, Uninitialized scalar variable by Justin Chadwell · Tue Jul 23 09:45:18 2019 +0100
  77. 90f2e88 Add support for Branch Target Identification by Alexei Fedorov · Fri May 24 12:17:09 2019 +0100
  78. bdfa103 MPAM: enable MPAM EL2 traps by Louis Mayencourt · Mon Feb 11 11:25:50 2019 +0000
  79. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  80. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  81. 5753e49 Mark BL31 initialization functions by Daniel Boulby · Thu Sep 20 14:12:46 2018 +0100
  82. 067a357 RAS: Fix assert condition by Jeenu Viswambharan · Fri Sep 07 16:30:58 2018 +0100
  83. 69ac42b Merge pull request #1532 from jeenu-arm/misra-fixes by Dimitris Papastamos · Wed Aug 22 10:25:41 2018 +0100
  84. 31ac01e RAS: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  85. 2da918c AArch64: Enable MPAM for lower ELs by Jeenu Viswambharan · Tue Jul 31 16:13:33 2018 +0100
  86. d51f80f RAS: ras_common: Add null pointer check for error record probe function by Sughosh Ganu · Sat May 12 11:02:31 2018 +0530
  87. d86cc5b RAS: Allow individual interrupt registration by Jeenu Viswambharan · Tue Dec 12 10:34:58 2017 +0000
  88. 2e2e881 RAS: Add support for node registration by Jeenu Viswambharan · Fri Dec 08 15:38:21 2017 +0000
  89. 19f6cf2 RAS: Add helpers to access Standard Error Records by Jeenu Viswambharan · Thu Dec 07 08:43:05 2017 +0000
  90. b8d8145 Merge pull request #1282 from robertovargas-arm/misra-changes by davidcunado-arm · Wed Feb 28 18:53:30 2018 +0000
  91. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  92. aaa1985 MISRA fixes for AMU/SPE and SVE by Dimitris Papastamos · Mon Feb 26 17:56:31 2018 +0000
  93. e0848e9 aarch32: Fix multiple bugs in amu_helpers.S by Dimitris Papastamos · Tue Feb 20 12:25:36 2018 +0000
  94. 430f115 Assert that group0/group1 counter config is what we expect by Dimitris Papastamos · Tue Feb 20 11:16:44 2018 +0000
  95. 5e8cd79 Implement {spe,sve}_supported() helpers and refactor code by Dimitris Papastamos · Mon Feb 19 14:52:19 2018 +0000
  96. 0dcdd8d AMU: Implement context save/restore for aarch32 by Joel Hutton · Thu Dec 21 15:21:20 2017 +0000
  97. 2691bc6 AMU: Add assembler helper functions for aarch32 by Joel Hutton · Tue Dec 12 15:47:55 2017 +0000
  98. 7c4a6e6 AMU: Remove unnecessary WARN() by Dimitris Papastamos · Mon Jan 15 14:52:57 2018 +0000
  99. eaf3e6d AMU: Add hooks to save/restore AMU context by Dimitris Papastamos · Tue Nov 28 13:47:06 2017 +0000
  100. 525c37a AMU: Add configuration helpers for aarch64 by Dimitris Papastamos · Mon Nov 13 09:49:45 2017 +0000