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git01.mediatek.com / filogic / atf / a45433b2b9f40344f31642be3ca20910c480c9e4 / bl31 / aarch64 / bl31_entrypoint.S
  1. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  2. 4e28c20 PIE: Position Independant Executable support for BL31 by Soby Mathew · 6 years ago
  3. f0b14cf Remove some MISRA defects in common code by Antonio Nino Diaz · 6 years ago
  4. e834ee1 DynamIQ: Enable MMU without using stack by Jeenu Viswambharan · 7 years ago
  5. 9c274f8 Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch by davidcunado-arm · 7 years ago
  6. 7c2a3ca Add comments about mismatched TCR_ELx and xlat tables by Antonio Nino Diaz · 7 years ago
  7. 73308d0 Introduce the new BL handover interface by Soby Mathew · 7 years ago
  8. fee8653 Fully initialise essential control registers by David Cunado · 8 years ago
  9. fa3cf0b Use SPDX license identifiers by dp-arm · 8 years ago
  10. 043fe9c PSCI: Build option to enable D-Caches early in warmboot by Soby Mathew · 8 years ago
  11. 1fecc8d Merge pull request #860 from jeenu-arm/hw-asstd-coh by davidcunado-arm · 8 years ago
  12. 4ef91f1 Simplify translation tables headers dependencies by Antonio Nino Diaz · 8 years ago
  13. 4614496 Enable data caches early with hardware-assisted coherency by Jeenu Viswambharan · 8 years ago
  14. 3cac786 Add PMF instrumentation points in TF by dp-arm · 8 years ago
  15. d019487 Introduce PSCI Library Interface by Soby Mathew · 9 years ago
  16. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · 9 years ago
  17. b21b02f Introduce COLD_BOOT_SINGLE_CPU build option by Sandrine Bailleux · 9 years ago
  18. e9c4a64 Make generic code work in presence of system caches by Achin Gupta · 9 years ago
  19. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · 9 years ago
  20. acde8b0 Rationalize reset handling code by Sandrine Bailleux · 9 years ago
  21. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · 10 years ago
  22. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · 10 years ago
  23. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 10 years ago
  24. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · 10 years ago
  25. 046cd3f Miscellaneous documentation fixes by Sandrine Bailleux · 10 years ago
  26. 8e2f287 Add CPU specific power management operations by Soby Mathew · 10 years ago
  27. c704cbc Introduce framework for CPU specific operations by Soby Mathew · 10 years ago
  28. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · 10 years ago
  29. b3dbeb0 Call platform_is_primary_cpu() only from reset handler by Juan Castillo · 10 years ago
  30. 45c31c4 Merge pull request #172 from soby-mathew/sm/asm_assert by danh-arm · 10 years ago
  31. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · 10 years ago
  32. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · 10 years ago
  33. f4a9709 Remove coherent stack usage from the cold boot path by Achin Gupta · 10 years ago
  34. f268c72 Merge pull request #151 from vikramkanigiri/vk/t133-code-readability by Andrew Thoelke · 10 years ago
  35. cf79bf5 Simplify entry point information generation code on FVP by Vikram Kanigiri · 10 years ago
  36. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · 10 years ago
  37. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · 10 years ago
  38. 9cf2bb7 Introduce interrupt handling framework in BL3-1 by Achin Gupta · 11 years ago
  39. 9637745 Add support for BL3-1 as a reset vector by Vikram Kanigiri · 11 years ago
  40. da56743 Populate BL31 input parameters as per new spec by Vikram Kanigiri · 11 years ago
  41. a3a5e4a Rework handover interface between BL stages by Vikram Kanigiri · 10 years ago
  42. 9ceff0f Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1 by danh-arm · 11 years ago
  43. 6c5192a Preserve x19-x29 across world switch for exception handling by Soby Mathew · 11 years ago
  44. f977ed8 Access system registers directly in assembler by Andrew Thoelke · 11 years ago
  45. 42e75a7 Correct usage of data and instruction barriers by Andrew Thoelke · 11 years ago
  46. 2bd4ef2 Reduce deep nesting of header files by Dan Handley · 11 years ago
  47. 714a0d2 Make use of user/system includes more consistent by Dan Handley · 11 years ago
  48. 38bde41 Place assembler functions in separate sections by Andrew Thoelke · 11 years ago
  49. 35ca351 Add support for BL3-2 in BL3-1 by Achin Gupta · 11 years ago
  50. e4d084e Rework BL2 to BL3-1 hand over interface by Achin Gupta · 11 years ago
  51. caa8493 Add support for handling runtime service requests by Jeenu Viswambharan · 11 years ago
  52. b739f22 Setup VBAR_EL3 incrementally by Achin Gupta · 11 years ago
  53. 3a4cae0 Change comments in assembler files to help ctags by Jeenu Viswambharan · 11 years ago
  54. 4f60368 Do not trap access to floating point registers by Harry Liebel · 11 years ago
  55. e83b0ca Update year in copyright text to 2014 by Dan Handley · 11 years ago
  56. 93ca221 Make BL31's ns_entry_info a single-cpu area by Sandrine Bailleux · 11 years ago
  57. ba6980a Move RUN_IMAGE constant from bl1.h to bl_common.h by Sandrine Bailleux · 11 years ago
  58. ab2d31e Enable third party contributions by Dan Handley · 11 years ago
  59. 65f546a Properly initialise the C runtime environment by Sandrine Bailleux · 11 years ago
  60. 8d69a03 Various improvements/cleanups on the linker scripts by Sandrine Bailleux · 11 years ago
  61. c10bd2c Move generic architectural setup out of blx_plat_arch_setup(). by Sandrine Bailleux · 11 years ago
  62. 4f6ad66 ARMv8 Trusted Firmware release v0.2 by Achin Gupta · 11 years ago