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git01.mediatek.com / filogic / atf / 9f5a856d5a4abdf070f5ea61f2ec4a9bbe2ad86a / plat / nxp / s32
  1. 6fd400f Merge changes from topic "nxp-drivers/add-linflex-clk" into integration by Madhukar Pappireddy · Thu Aug 22 15:09:16 2024 +0200
  2. 0609bcd feat(nxp-clk): enable UART clock by Ghennadi Procopciuc · Tue Aug 06 13:25:51 2024 +0300
  3. 8b804e2 feat(nxp-drivers): add Linflex flush callback by Ghennadi Procopciuc · Tue Aug 06 23:41:45 2024 +0300
  4. f648e5d feat(s32g274a): enable BL2 early clocks by Ghennadi Procopciuc · Wed Jun 12 09:07:16 2024 +0300
  5. 7014cde feat(s32g274a): use s32cc clock driver by Ghennadi Procopciuc · Tue Jun 11 18:45:33 2024 +0300
  6. d3d6f54 fix(s32g274a): avoid overwriting const fields by Ghennadi Procopciuc · Fri May 10 15:17:57 2024 +0300
  7. 1e38cff feat(s32g274a): enable BL31 stage by Ghennadi Procopciuc · Fri Jan 26 15:29:08 2024 +0200
  8. a9fee05 feat(s32g274a): add S32G274ARDB2 board support by Ghennadi Procopciuc · Tue Jan 30 16:19:47 2024 +0200