Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 9bc79791b2c1181b424567a1ff8e874d2d894a4c / drivers / nxp / clk / s32cc / include / s32cc-clk-regs.h
  1. d89e32f feat(nxp-clk): enable the DDR clock by Ghennadi Procopciuc · Tue Sep 17 11:22:30 2024 +0300
  2. 74dde09 feat(nxp-clk): setup the DDR PLL by Ghennadi Procopciuc · Mon Sep 09 10:24:35 2024 +0300
  3. 22f9474 feat(nxp-clk): add PERIPH PLL enablement by Ghennadi Procopciuc · Tue Aug 06 11:48:11 2024 +0300
  4. 90c9000 feat(nxp-clk): add CGM0 instance by Ghennadi Procopciuc · Mon Aug 05 16:50:52 2024 +0300
  5. f21d3ae feat(nxp-clk): add DFS module enablement by Ghennadi Procopciuc · Mon Aug 05 16:48:49 2024 +0300
  6. a080f78 feat(nxp-clk): enable the A53 clock by Ghennadi Procopciuc · Wed Jun 12 14:44:47 2024 +0300
  7. b390c4d feat(nxp-clk): add ARM PLL enablement by Ghennadi Procopciuc · Wed Jun 12 14:21:39 2024 +0300
  8. 9dee8e4 feat(nxp-clk): add FXOSC clock enablement by Ghennadi Procopciuc · Wed Jun 12 09:25:17 2024 +0300