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git01.mediatek.com / filogic / atf / 961f7f108d3052c5cfffdc60cac70a88fb6ecf93 / plat / intel / soc / n5x / include / n5x_clock_manager.h
  1. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · 12 months ago
  2. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 7 months ago
  3. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years ago