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git01.mediatek.com / filogic / atf / 8d1ade665cc7903e6afc7549b568199dcb23392a / plat / renesas / rcar / bl2_plat_setup.c
  1. 4d693c2 plat: rcar: Generate FCNL reserved memory node by Marek Vasut · 6 years ago
  2. a987b00 plat: rcar: Generate platform compatible string by Marek Vasut · 6 years ago
  3. 93c85fc plat: rcar: Pass DTB with DRAM layout from BL2 to next stages by Marek Vasut · 6 years ago
  4. 6a6881a plat: rcar: Use array in the DRAM size reporting by Marek Vasut · 6 years ago
  5. 63659fd plat: rcar: Print DRAM configuration after init by Marek Vasut · 6 years ago
  6. 9963f70 plat: rcar: Fill in memory information for M3W, M3N by Marek Vasut · 6 years ago
  7. b0e1359 plat: rcar: Drop H3 v3.0 check on DRAM debug print by Marek Vasut · 6 years ago
  8. 8cb12ec plat: rcar: Add E3 1GBx4 debug print by Marek Vasut · 6 years ago
  9. 673bc32 plat: rcar: Move DRAM layout print to separate function by Marek Vasut · 6 years ago
  10. bf084dc rcar-gen3: initial commit for the rcar-gen3 boards by Jorge Ramirez-Ortiz · 6 years ago