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git01.mediatek.com / filogic / atf / 8186596b15f80a647f49555d1f1a934a41be13ea / lib / cpus / aarch32
  1. 7f7c6fa fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960 by John Powell · Thu Apr 14 19:10:17 2022 -0500
  2. b580095 lib: cpus: aarch32: sanity check pointers before use by Yann Gautier · Tue Feb 23 14:50:44 2021 +0100
  3. 26d1676 Cortex A9:errata 794073 workaround by Joel Hutton · Wed Apr 10 12:52:52 2019 +0100
  4. fa5c951 Cortex-A17: Implement workaround for errata 852423 by Ambroise Vincent · Mon Mar 04 13:20:56 2019 +0000
  5. 8cf9eef Cortex-A17: Implement workaround for errata 852421 by Ambroise Vincent · Thu Feb 28 16:23:53 2019 +0000
  6. 68b3812 Cortex-A15: Implement workaround for errata 827671 by Ambroise Vincent · Tue Mar 05 09:54:21 2019 +0000
  7. d4a51eb Cortex-A15: Implement workaround for errata 816470 by Ambroise Vincent · Mon Mar 04 16:56:26 2019 +0000
  8. dbb0db6 Fixup register handling in aarch32 reset_handler by Heiko Stuebner · Wed Mar 06 00:29:13 2019 +0100
  9. fb6f2fc Merge pull request #1751 from vwadekar/tegra-scatter-file-support by Antonio Niño Díaz · Fri Mar 01 11:23:58 2019 +0000
  10. f5fdfbc Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · Thu Feb 21 14:16:24 2019 +0000
  11. aa2c029 Cortex-A57: Implement workaround for erratum 817169 by Ambroise Vincent · Thu Feb 21 16:35:49 2019 +0000
  12. 1b0db76 Cortex-A57: Implement workaround for erratum 814670 by Ambroise Vincent · Thu Feb 21 16:35:07 2019 +0000
  13. 4d034c5 Tegra: Support for scatterfile for the BL31 image by Varun Wadekar · Fri Jan 11 14:47:48 2019 -0800
  14. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  15. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  16. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  17. d1e1930 Fixup AArch32 errata printing framework by Soby Mathew · Wed Feb 21 15:48:03 2018 +0000
  18. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  19. 471fb9b Merge pull request #1229 from manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix by davidcunado-arm · Sat Jan 20 17:04:49 2018 +0000
  20. e37c029 lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode by Manoj Kumar · Fri Jan 19 17:51:31 2018 +0530
  21. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  22. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  23. 4c24bb7 Merge pull request #1168 from matt2048/master by davidcunado-arm · Mon Dec 04 22:39:40 2017 +0000
  24. 41b0094 Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS by Matt Ma · Wed Nov 22 19:31:28 2017 +0800
  25. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  26. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  27. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  28. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  29. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  30. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  31. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  32. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  33. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  34. 2b40ca6 aarch32: Implement errata workarounds for Cortex A57 by Dimitris Papastamos · Mon Jun 05 14:55:41 2017 +0100
  35. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  36. 370542e aarch32: Implement cpu_rev_var_hs() by Dimitris Papastamos · Mon Jun 05 13:36:34 2017 +0100
  37. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  38. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  39. bf360df Merge pull request #910 from dp-arm/dp/AArch32-juno-port by davidcunado-arm · Fri Apr 21 17:10:27 2017 +0100
  40. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  41. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · Thu Apr 20 09:58:28 2017 +0100
  42. 9d92e8c Replace ASM signed tests with unsigned by Douglas Raillard · Tue Mar 07 16:36:14 2017 +0000
  43. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  44. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  45. ee5eb80 Add provision to extend CPU operations at more levels by Jeenu Viswambharan · Fri Nov 18 12:58:28 2016 +0000
  46. adb7027 AArch32: Fix the stack alignment issue by Soby Mathew · Tue Dec 06 12:10:51 2016 +0000
  47. a4c219a AArch32: Add support for ARM Cortex-A32 MPCore Processor by Yatharth Kochar · Tue Jul 12 15:47:03 2016 +0100
  48. f528faf AArch32: Common changes needed for BL1/BL2 by Yatharth Kochar · Tue Jun 28 16:58:26 2016 +0100
  49. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100