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git01.mediatek.com / filogic / atf / 7c75489b11198fd259115e9ed651550420a12748 / lib / el3_runtime / aarch64 / context_mgmt.c
  1. 1d8795e refactor(context-mgmt): move FEAT_HCX save/restore into C by Andre Przywara · Tue Nov 15 11:45:19 2022 +0000
  2. 5d6d2ab refactor(context-mgmt): move FEAT_FGT save/restore code into C by Andre Przywara · Thu Nov 10 14:40:37 2022 +0000
  3. e8920f6 refactor(cpufeat): decouple FGT feature detection and build flags by Andre Przywara · Thu Nov 10 14:28:01 2022 +0000
  4. 181dafb Merge "fix(pmu): add sensible default for MDCR_EL2" into integration by Manish Pandey · Fri Nov 11 16:56:30 2022 +0100
  5. ecd9f08 fix(pmu): add sensible default for MDCR_EL2 by Boyan Karatotev · Wed Oct 26 15:10:39 2022 +0100
  6. 0e3379d fix(ras): restrict RAS support for NS world by Manish Pandey · Mon Oct 10 11:43:08 2022 +0100
  7. 7c6fcb4 fix(ras): trap "RAS error record" accesses only for NS by Manish Pandey · Tue Sep 27 14:30:34 2022 +0100
  8. 785e66c refactor(libc): clean up dependencies in libc by Claus Pedersen · Mon Sep 12 22:42:58 2022 +0000
  9. cc238bb fix(context mgmt): remove explicit ICC_SRE_EL2 register read by Varun Wadekar · Tue Sep 13 12:38:47 2022 +0100
  10. 42305f2 feat(rng-trap): add EL3 support for FEAT_RNG_TRAP by Juan Pablo Conde · Tue Jul 12 16:40:29 2022 -0400
  11. 5362beb refactor(context mgmt): refactor EL2 context save and restore functions by Zelalem Aweke · Mon Apr 04 17:42:48 2022 -0500
  12. 2012600 refactor(context mgmt): refactor initialization of EL1 context registers by Zelalem Aweke · Fri Apr 08 16:48:05 2022 -0500
  13. 8a48954 Merge "fix(amu): limit virtual offset register access to NS world" into integration by Joanna Farley · Tue May 10 15:55:05 2022 +0200
  14. e43ba98 Merge "fix(cm): add barrier before el3 ns exit" into integration by Olivier Deprez · Tue May 10 14:15:51 2022 +0200
  15. e4793dd fix(cm): add barrier before el3 ns exit by Olivier Deprez · Mon May 09 17:34:02 2022 +0200
  16. 8186596 feat(brbe): add BRBE support for NS world by johpow01 · Fri Jan 28 17:06:20 2022 -0600
  17. cc79927 fix(amu): limit virtual offset register access to NS world by John Powell · Tue Mar 29 00:25:59 2022 -0500
  18. 4b5489c refactor(twed): improve TWED enablement in EL-3 by Jayanth Dodderi Chidanand · Mon Mar 28 15:28:55 2022 +0100
  19. f92c0cb refactor(context mgmt): add cm_prepare_el3_exit_ns function by Zelalem Aweke · Mon Jan 31 16:59:42 2022 -0600
  20. 4240111 refactor(context mgmt): refactor the cm_setup_context function by Zelalem Aweke · Wed Jan 05 17:12:24 2022 -0600
  21. 9baade3 feat(sme): enable SME functionality by johpow01 · Thu Jul 08 14:14:00 2021 -0500
  22. b6301e6 feat(rme): add context management changes for FEAT_RME by Zelalem Aweke · Fri Jul 09 17:54:30 2021 -0500
  23. f91e59f feat(hcx): add build option to enable FEAT_HCX by johpow01 · Wed Aug 04 19:38:18 2021 -0500
  24. 51a9711 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · Thu Jul 08 09:33:18 2021 +0100
  25. f356f7e feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · Tue Jun 29 11:44:20 2021 +0100
  26. 20df29c feat(trbe): enable access to trace buffer control registers from lower NS EL by Manish V Badarkhe · Fri Jul 02 09:10:56 2021 +0100
  27. e1cccb4 feat(trbe): initialize trap settings of trace buffer control registers access by Manish V Badarkhe · Wed Jun 23 20:02:39 2021 +0100
  28. cac7d16 fix(el3_runtime): fix SVE and AMU extension enablement flags by Arunachalam Ganapathy · Thu Jul 08 09:35:57 2021 +0100
  29. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
  30. 7d0299f fix: random typos in tf-a code base by Olivier Deprez · Tue May 25 12:06:03 2021 +0200
  31. fa59c6f Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · Fri Oct 02 13:41:11 2020 -0500
  32. af54f6e Aarch64: Add support for FEAT_MTE3 by Alexei Fedorov · Tue Dec 01 13:22:25 2020 +0000
  33. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · Tue Aug 04 16:18:52 2020 -0500
  34. 4283ed1 SPM: Change condition on saving/restoring EL2 registers by Ruari Phipps · Tue Jul 28 11:26:29 2020 +0100
  35. 9223485 Prevent RAS register access from lower ELs by Varun Wadekar · Fri Jun 12 10:11:28 2020 -0700
  36. 8357389 Enable ARMv8.6-ECV Self-Synch when booting to EL2 by Jimmy Brisson · Thu Apr 16 10:48:02 2020 -0500
  37. ecc3c67 Enable ARMv8.6-FGT when booting to EL2 by Jimmy Brisson · Thu Apr 16 10:47:56 2020 -0500
  38. 3e24c16 Enable v8.6 WFE trap delays by johpow01 · Wed Apr 22 14:05:13 2020 -0500
  39. c9e2c92 SPMD: Adds partially supported EL2 registers. by Max Shvetsov · Mon Feb 17 16:15:47 2020 +0000
  40. bdf502d SPMD: save/restore EL2 system registers. by Max Shvetsov · Tue Feb 25 13:56:19 2020 +0000
  41. 87675d4 Coverity: remove unnecessary header file includes by Zelalem · Mon Feb 03 14:56:42 2020 -0600
  42. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  43. a533447 S-EL2 Support: Check for AArch64 by Artsem Artsemenka · Tue Nov 26 16:40:31 2019 +0000
  44. 023c155 Add support for enabling S-EL2 by Achin Gupta · Fri Oct 11 14:44:05 2019 +0100
  45. 05e030e Fix MTE support from causing unused variable warnings by Justin Chadwell · Fri Sep 20 09:13:14 2019 +0100
  46. b0f2602 SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64 by Deepika Bhavnani · Tue Sep 03 21:08:51 2019 +0300
  47. 1c7c13a Enable MTE support in both secure and non-secure worlds by Justin Chadwell · Thu Jul 18 14:25:33 2019 +0100
  48. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  49. 830f0ad Enable MTE support unilaterally for Normal World by Soby Mathew · Fri Jul 12 09:23:38 2019 +0100
  50. 23b7b69 Merge pull request #1839 from loumay-arm/lm/a7x_errata by Antonio Niño Díaz · Thu Feb 28 10:19:24 2019 +0000
  51. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
  52. 78a0aed Add workaround for errata 764081 of Cortex-A75 by Louis Mayencourt · Wed Feb 20 12:11:41 2019 +0000
  53. 1fbc97b Correct typographical errors by Paul Beesley · Fri Jan 11 18:26:51 2019 +0000
  54. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  55. 864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
  56. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  57. cbad661 AArch64: Enable lower ELs to use pointer authentication by Jeenu Viswambharan · Wed Aug 15 14:29:29 2018 +0100
  58. 5753e49 Mark BL31 initialization functions by Daniel Boulby · Thu Sep 20 14:12:46 2018 +0100
  59. c51a2ec context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation by Julius Werner · Tue Aug 28 14:45:43 2018 -0700
  60. 2da918c AArch64: Enable MPAM for lower ELs by Jeenu Viswambharan · Tue Jul 31 16:13:33 2018 +0100
  61. 28dce9e context_mgmt: Make cm_init_context_common public by Antonio Nino Diaz · Tue May 22 10:09:10 2018 +0100
  62. b2f1003 Merge pull request #1376 from vwadekar/cm-init-actlr-el1 by Dimitris Papastamos · Tue May 15 18:40:46 2018 +0100
  63. b6dd0b3 lib: el3_runtime: initialise actlr_el1 to hardware defaults by Varun Wadekar · Tue May 08 10:52:36 2018 -0700
  64. f00da74 RAS: Add fault injection support by Jeenu Viswambharan · Fri Dec 08 12:13:51 2017 +0000
  65. 3c817f4 Rename 'smcc' to 'smccc' by Antonio Nino Diaz · Wed Mar 21 10:49:27 2018 +0000
  66. ce88eee Enable SVE for Non-secure world by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  67. e08005a AMU: Implement support for aarch64 by Dimitris Papastamos · Thu Oct 12 13:02:29 2017 +0100
  68. 5bdbb47 Refactor Statistical Profiling Extensions implementation by Dimitris Papastamos · Fri Oct 13 12:06:06 2017 +0100
  69. 1e6f93e Factor out extension enabling to a separate function by Dimitris Papastamos · Tue Nov 07 09:55:29 2017 +0000
  70. a7921b9 aarch64: Add PubSub events to capture security state transitions by Dimitris Papastamos · Fri Oct 13 15:27:58 2017 +0100
  71. 4168f2f Init and save / restore of PMCR_EL0 / PMCR by David Cunado · Mon Oct 02 17:41:39 2017 +0100
  72. 00eac15 fix a typo about sctlr_el2 by Ken Kuang · Wed Aug 23 16:03:29 2017 +0800
  73. ee3457b aarch64: Enable Statistical Profiling Extensions for lower ELs by dp-arm · Tue May 23 09:32:49 2017 +0100
  74. fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
  75. 6715485 Merge pull request #927 from jeenu-arm/state-switch by davidcunado-arm · Thu May 11 16:04:52 2017 +0100
  76. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  77. 2a9b882 Add macro to check whether the CPU implements an EL by Jeenu Viswambharan · Tue Feb 21 14:40:44 2017 +0000
  78. a8954fc Replace some memset call by zeromem by Douglas Raillard · Thu Jan 26 15:54:44 2017 +0000
  79. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900
  80. c14b08e Reset EL2 and EL3 configurable controls by David Cunado · Fri Nov 25 00:21:59 2016 +0000
  81. 5f55e28 Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR by David Cunado · Mon Oct 31 17:37:34 2016 +0000
  82. a993c42 Unify SCTLR initialization for AArch32 normal world by Soby Mathew · Thu Sep 29 14:15:57 2016 +0100
  83. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000[Renamed from common/context_mgmt.c]
  84. a0fedc4 Rework type usage in Trusted Firmware by Soby Mathew · Thu Jun 16 14:52:04 2016 +0100
  85. a3b3c05 context: Fix typo in comment by Soren Brinkmann · Mon Apr 18 10:46:19 2016 -0700
  86. 632d6df Enable asynchronous abort exceptions during boot by Gerald Lejeune · Tue Mar 22 09:29:23 2016 +0100
  87. 6c0566c Move context management code to common location by Yatharth Kochar · Fri Oct 02 17:56:48 2015 +0100[Renamed (77%) from bl31/context_mgmt.c]
  88. e58ddc0 Merge pull request #461 from yatharth-arm/yk/nvidia_patch by danh-arm · Wed Dec 09 16:15:23 2015 +0000