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git01.mediatek.com / filogic / atf / 738df262dfd64e9d4f5d840a7c2ef8fd019ceebe / bl31 / aarch64
  1. 7690382 Move assembly newline function into common debug code by Justin Chadwell · Tue Aug 20 10:58:49 2019 +0100
  2. c7a7cc3 Merge "AArch64: Disable Secure Cycle Counter" into integration by Paul Beesley · Fri Aug 23 11:26:57 2019 +0000
  3. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  4. c4dfb3b AArch64: Align crash reporting output by Alexei Fedorov · Mon Jul 29 13:34:07 2019 +0100
  5. b5b903c Fix BL31 crash reporting on AArch64 only machines by Imre Kis · Mon Jul 22 11:56:45 2019 +0200
  6. 90f2e88 Add support for Branch Target Identification by Alexei Fedorov · Fri May 24 12:17:09 2019 +0100
  7. d87233a Rework smc_unknown return code path in smc_handler by Madhukar Pappireddy · Wed May 08 15:41:41 2019 -0500
  8. dd894cc Fix restoration of PAuth context by Alexei Fedorov · Fri Apr 05 13:44:30 2019 +0100
  9. 81de7ab PIE: Fix reloc at the beginning of bl31 entrypoint by Louis Mayencourt · Fri Mar 22 16:33:23 2019 +0000
  10. 3287c4f Restore PAuth context in case of unknown SMC call by Alexei Fedorov · Mon Mar 18 15:59:34 2019 +0000
  11. e71d26c BL31: Enable pointer authentication support in warm boot path by Alexei Fedorov · Wed Mar 06 11:15:51 2019 +0000
  12. 47a9064 BL31: Enable pointer authentication support by Antonio Nino Diaz · Thu Jan 31 11:01:26 2019 +0000
  13. 25cda67 Add support for pointer authentication by Antonio Nino Diaz · Tue Feb 19 11:53:51 2019 +0000
  14. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
  15. 0e402d3 Remove support for the SMC Calling Convention 2.0 by Antonio Nino Diaz · Wed Jan 30 16:01:49 2019 +0000
  16. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  17. f939a6a SPM: Introduce SMC handlers for SPCI and SPRT by Antonio Nino Diaz · Thu Nov 08 14:12:40 2018 +0000
  18. d1198ad BL31: Use helper function to save registers in SMC handler by Soby Mathew · Fri Nov 16 15:43:34 2018 +0000
  19. 4e28c20 PIE: Position Independant Executable support for BL31 by Soby Mathew · Sun Oct 14 08:09:22 2018 +0100
  20. f0b14cf Remove some MISRA defects in common code by Antonio Nino Diaz · Thu Oct 04 09:55:23 2018 +0100
  21. 911fcc9 RAS: Introduce handler for EL3 EAs by Jeenu Viswambharan · Fri Jul 06 16:50:06 2018 +0100
  22. 93bc4bd RAS: Introduce handler for Double Faults by Jeenu Viswambharan · Thu May 17 11:24:01 2018 +0100
  23. 9d4c9c1 RAS: Introduce handler for Uncontainable errors by Jeenu Viswambharan · Thu May 17 09:52:36 2018 +0100
  24. 476c29f RAS: Validate stack pointer after error handling by Jeenu Viswambharan · Mon Feb 19 12:25:53 2018 +0000
  25. e86a247 RAS: Move EA handling to a separate file by Jeenu Viswambharan · Thu Jul 05 15:24:45 2018 +0100
  26. 95f30ab Add end_vector_entry assembler macro by Roberto Vargas · Tue Apr 17 11:31:43 2018 +0100
  27. e834ee1 DynamIQ: Enable MMU without using stack by Jeenu Viswambharan · Fri Apr 27 15:17:03 2018 +0100
  28. 9a7ce2f AArch64: Introduce RAS handling by Jeenu Viswambharan · Wed Apr 04 16:07:11 2018 +0100
  29. 96c7df0 AArch64: Introduce External Abort handling by Jeenu Viswambharan · Thu Nov 30 12:54:15 2017 +0000
  30. 23d05a8 AArch64: Refactor GP register restore to separate function by Jeenu Viswambharan · Wed Nov 29 16:59:34 2017 +0000
  31. 35c8cfc Add support for the SMC Calling Convention 2.0 by Antonio Nino Diaz · Mon Apr 23 15:43:29 2018 +0100
  32. 9c274f8 Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch by davidcunado-arm · Wed Feb 28 01:26:21 2018 +0000
  33. 7c2a3ca Add comments about mismatched TCR_ELx and xlat tables by Antonio Nino Diaz · Fri Feb 23 15:07:54 2018 +0000
  34. 73308d0 Introduce the new BL handover interface by Soby Mathew · Tue Jan 09 14:36:14 2018 +0000
  35. e4794b7 Redefine SMC_UNK as -1 instead of 0xFFFFFFFF by Antonio Nino Diaz · Wed Feb 14 14:22:29 2018 +0000
  36. 0415951 runtime_exceptions: Save x4-x29 unconditionally by Dimitris Papastamos · Mon Jan 22 11:53:04 2018 +0000
  37. d79d40d Merge pull request #1193 from jwerner-chromium/JW_coreboot by davidcunado-arm · Wed Jan 24 14:31:53 2018 +0000
  38. 446f7f1 Workaround for CVE-2017-5715 on Cortex A57 and A72 by Dimitris Papastamos · Thu Nov 30 14:53:53 2017 +0000
  39. 02eb727 utils_def: Add REGSZ and make BIT() assembly-compatible by Julius Werner · Tue Dec 12 14:23:26 2017 -0800
  40. d1a1fd4 Move FPEXC32_EL2 to FP Context by David Cunado · Fri Oct 20 11:30:57 2017 +0100
  41. 67ebde7 Fix x30 reporting for unhandled exceptions by Julius Werner · Thu Jul 27 14:59:34 2017 -0700
  42. fee8653 Fully initialise essential control registers by David Cunado · Thu Apr 13 22:38:29 2017 +0100
  43. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  44. 043fe9c PSCI: Build option to enable D-Caches early in warmboot by Soby Mathew · Mon Apr 10 22:35:42 2017 +0100
  45. d3ec543 Add and use plat_crash_console_flush() API by Antonio Nino Diaz · Fri Feb 17 17:11:27 2017 +0000
  46. 1fecc8d Merge pull request #860 from jeenu-arm/hw-asstd-coh by davidcunado-arm · Fri Mar 17 12:34:37 2017 +0000
  47. 4ef91f1 Simplify translation tables headers dependencies by Antonio Nino Diaz · Mon Feb 20 14:22:22 2017 +0000
  48. 4614496 Enable data caches early with hardware-assisted coherency by Jeenu Viswambharan · Thu Jan 05 10:37:21 2017 +0000
  49. 68aef10 Define and use no_ret macro where no return is expected by Jeenu Viswambharan · Wed Nov 30 15:21:11 2016 +0000
  50. 0980eed Cosmetic change to exception table by Douglas Raillard · Wed Nov 09 17:48:27 2016 +0000
  51. 3cac786 Add PMF instrumentation points in TF by dp-arm · Mon Sep 19 11:18:44 2016 +0100
  52. d019487 Introduce PSCI Library Interface by Soby Mathew · Fri Apr 29 19:01:30 2016 +0100
  53. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000
  54. 9e6ad6c Introduce some helper macros for exception vectors by Sandrine Bailleux · Tue May 24 16:56:03 2016 +0100
  55. 391a76e Add 32 bit version of plat_get_syscnt_freq by Antonio Nino Diaz · Wed May 18 16:53:31 2016 +0100
  56. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · Thu Nov 26 15:47:53 2015 +0100
  57. 851dc7e Add ISR_EL1 to crash report by Gerald Lejeune · Tue Mar 22 11:11:46 2016 +0100
  58. 632d6df Enable asynchronous abort exceptions during boot by Gerald Lejeune · Tue Mar 22 09:29:23 2016 +0100
  59. 1f21bcf Remove all non-configurable dead loops by Antonio Nino Diaz · Mon Feb 01 13:57:25 2016 +0000
  60. f4119ec Miscellaneous doc fixes for v1.2 by Sandrine Bailleux · Thu Dec 17 13:58:58 2015 +0000
  61. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · Mon Dec 14 09:35:25 2015 +0000
  62. 6c0566c Move context management code to common location by Yatharth Kochar · Fri Oct 02 17:56:48 2015 +0100
  63. e77e116 Fix issue in Floating point register restore by Soby Mathew · Thu Dec 03 09:42:50 2015 +0000
  64. 8f67649 Merge pull request #443 from achingupta/sb/el3_payloads-cb_single_cpu by danh-arm · Tue Dec 01 19:02:24 2015 +0000
  65. b21b02f Introduce COLD_BOOT_SINGLE_CPU build option by Sandrine Bailleux · Fri Oct 30 15:05:17 2015 +0000
  66. c5204fa Remove the IMF_READ_INTERRUPT_ID build option by Soby Mathew · Tue Oct 27 10:01:06 2015 +0000
  67. e9c4a64 Make generic code work in presence of system caches by Achin Gupta · Fri Sep 11 16:03:13 2015 +0100
  68. 3700a92 PSCI: Migrate TF to the new platform API and CM helpers by Soby Mathew · Mon Jul 13 11:21:11 2015 +0100
  69. 9ccbc03 Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1 by danh-arm · Wed Jun 24 11:23:33 2015 +0100
  70. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · Tue Jun 02 17:19:43 2015 +0100
  71. acde8b0 Rationalize reset handling code by Sandrine Bailleux · Tue May 19 11:54:45 2015 +0100
  72. 979992e Fix handling of spurious interrupts in BL3_1 by Achin Gupta · Wed May 13 17:57:18 2015 +0100
  73. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · Tue Mar 24 14:03:57 2015 +0000
  74. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  75. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  76. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · Thu Jan 08 18:02:44 2015 +0000
  77. 046cd3f Miscellaneous documentation fixes by Sandrine Bailleux · Wed Aug 06 11:27:23 2014 +0100
  78. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  79. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  80. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100
  81. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · Mon Aug 04 23:13:10 2014 +0100
  82. 534ae7f Merge pull request #179 from jcastillo-arm/jc/tf-issues/219 by danh-arm · Mon Aug 04 10:34:18 2014 +0100
  83. b3dbeb0 Call platform_is_primary_cpu() only from reset handler by Juan Castillo · Wed Jul 16 15:53:43 2014 +0100
  84. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · Fri Jul 04 16:02:26 2014 +0100
  85. 45c31c4 Merge pull request #172 from soby-mathew/sm/asm_assert by danh-arm · Mon Jul 28 14:28:40 2014 +0100
  86. 0da9593 Add CPUECTLR_EL1 and Snoop Control register to crash reporting by Soby Mathew · Wed Jul 16 09:23:52 2014 +0100
  87. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · Wed Jun 25 10:07:40 2014 +0100
  88. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · Fri Jul 18 18:38:28 2014 +0100
  89. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · Thu Jun 26 09:58:52 2014 +0100
  90. f4a9709 Remove coherent stack usage from the cold boot path by Achin Gupta · Wed Jun 25 19:26:22 2014 +0100
  91. 258e94f Allow FP register context to be optional at build time by Juan Castillo · Wed Jun 25 17:26:36 2014 +0100
  92. f268c72 Merge pull request #151 from vikramkanigiri/vk/t133-code-readability by Andrew Thoelke · Fri Jun 27 14:10:04 2014 +0100
  93. cf79bf5 Simplify entry point information generation code on FVP by Vikram Kanigiri · Mon Jun 02 14:59:00 2014 +0100
  94. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  95. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · Mon Jun 02 12:38:12 2014 +0100
  96. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100
  97. e385767 Merge pull request #133 from athoelke/at/crash-reporting-opt by danh-arm · Mon Jun 16 12:45:08 2014 +0100
  98. 385f4d4 Make the BL3-1 crash reporting optional by Andrew Thoelke · Tue Jun 03 11:50:53 2014 +0100
  99. af1ef2b Include 'platform_def.h' header file in 'crash_reporting.S' by Sandrine Bailleux · Tue May 27 15:46:07 2014 +0100
  100. 93c89ec Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · Wed May 28 17:14:36 2014 +0100