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git01.mediatek.com / filogic / atf / 65f43f5fa898ce5d96681e4f549a34b42c28c090 / bl31
  1. 68aef10 Define and use no_ret macro where no return is expected by Jeenu Viswambharan · Wed Nov 30 15:21:11 2016 +0000
  2. 0980eed Cosmetic change to exception table by Douglas Raillard · Wed Nov 09 17:48:27 2016 +0000
  3. c9ed717 Merge pull request #724 from rockchip-linux/support-rk3399-sdram by davidcunado-arm · Wed Oct 26 09:54:36 2016 +0100
  4. d90f43e rockchip: optimize the link mechanism for SRAM code by Caesar Wang · Tue Oct 11 09:36:00 2016 +0800
  5. 3cac786 Add PMF instrumentation points in TF by dp-arm · Mon Sep 19 11:18:44 2016 +0100
  6. 8da8966 PSCI: Do psci_setup() as part of std_svc_setup() by Soby Mathew · Mon Sep 19 17:21:15 2016 +0100
  7. 89256b8 PSCI: Introduce PSCI Library argument structure by Soby Mathew · Tue Sep 13 14:19:08 2016 +0100
  8. d019487 Introduce PSCI Library Interface by Soby Mathew · Fri Apr 29 19:01:30 2016 +0100
  9. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000
  10. a0fedc4 Rework type usage in Trusted Firmware by Soby Mathew · Thu Jun 16 14:52:04 2016 +0100
  11. f91f144 Introduce SEPARATE_CODE_AND_RODATA build flag by Sandrine Bailleux · Fri Jul 08 14:37:40 2016 +0100
  12. 241ec6c Add optional PSCI STAT residency & count functions by Yatharth Kochar · Mon May 09 18:26:35 2016 +0100
  13. 9518d02 Add Performance Measurement Framework(PMF) by Yatharth Kochar · Fri Mar 11 14:20:19 2016 +0000
  14. a913dee Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs by danh-arm · Fri Jun 03 15:12:37 2016 +0100
  15. d75d2ba Build option to include AArch32 registers in cpu context by Soby Mathew · Tue May 17 14:01:32 2016 +0100
  16. 9e6ad6c Introduce some helper macros for exception vectors by Sandrine Bailleux · Tue May 24 16:56:03 2016 +0100
  17. 391a76e Add 32 bit version of plat_get_syscnt_freq by Antonio Nino Diaz · Wed May 18 16:53:31 2016 +0100
  18. 2c7ed5b Dump platform-defined regs in crash reporting by Gerald Lejeune · Thu Nov 26 15:47:53 2015 +0100
  19. 851dc7e Add ISR_EL1 to crash report by Gerald Lejeune · Tue Mar 22 11:11:46 2016 +0100
  20. 632d6df Enable asynchronous abort exceptions during boot by Gerald Lejeune · Tue Mar 22 09:29:23 2016 +0100
  21. 1f21bcf Remove all non-configurable dead loops by Antonio Nino Diaz · Mon Feb 01 13:57:25 2016 +0000
  22. b3a0a7b Add support for %p in tf_printf() by Antonio Nino Diaz · Tue Feb 02 12:03:38 2016 +0000
  23. f4119ec Miscellaneous doc fixes for v1.2 by Sandrine Bailleux · Thu Dec 17 13:58:58 2015 +0000
  24. 7d19941 Remove dashes from image names: 'BL3-x' --> 'BL3x' by Juan Castillo · Mon Dec 14 09:35:25 2015 +0000
  25. 6e8f0b1 Merge pull request #462 from soby-mathew/sm/runtime_console by danh-arm · Wed Dec 09 19:03:06 2015 +0000
  26. 6c0566c Move context management code to common location by Yatharth Kochar · Fri Oct 02 17:56:48 2015 +0100
  27. 1ff495b Ensure BL31 does not print to boot console by default by Soby Mathew · Wed Dec 09 11:28:43 2015 +0000
  28. e6c3240 Merge pull request #460 from sandrine-bailleux/sb/init-vttbrel2-vmid by danh-arm · Wed Dec 09 15:16:08 2015 +0000
  29. 8b0eafe Initialize VTTBR_EL2 when bypassing EL2 by Sandrine Bailleux · Wed Nov 25 17:00:44 2015 +0000
  30. 1301122 Merge pull request #457 from soby-mathew/sm/fix_fpregs_restore by danh-arm · Wed Dec 09 11:27:12 2015 +0000
  31. e77e116 Fix issue in Floating point register restore by Soby Mathew · Thu Dec 03 09:42:50 2015 +0000
  32. 58e32d1 Enable support for EL3 interrupt in IMF by Soby Mathew · Mon Nov 23 13:58:45 2015 +0000
  33. 8f67649 Merge pull request #443 from achingupta/sb/el3_payloads-cb_single_cpu by danh-arm · Tue Dec 01 19:02:24 2015 +0000
  34. b21b02f Introduce COLD_BOOT_SINGLE_CPU build option by Sandrine Bailleux · Fri Oct 30 15:05:17 2015 +0000
  35. c5204fa Remove the IMF_READ_INTERRUPT_ID build option by Soby Mathew · Tue Oct 27 10:01:06 2015 +0000
  36. 18a6204 Replace build macro WARN_DEPRECATED with ERROR_DEPRECATED by Soby Mathew · Mon Oct 26 14:29:21 2015 +0000
  37. 489c939 Merge pull request #424 from jcastillo-arm/jc/tf-issues/327 by Achin Gupta · Tue Nov 10 13:46:00 2015 +0000
  38. 53c5184 IMF: postpone SCR_EL3 update if context is not initialized by Juan Castillo · Fri Oct 30 14:53:24 2015 +0000
  39. b2e224c Introduce print_entry_point_info() function by Sandrine Bailleux · Mon Sep 28 17:03:06 2015 +0100
  40. 405fafe Fix relocation of __PERCPU_BAKERY_LOCK_SIZE__ by Vikram Kanigiri · Thu Sep 24 15:45:43 2015 +0100
  41. e9c4a64 Make generic code work in presence of system caches by Achin Gupta · Fri Sep 11 16:03:13 2015 +0100
  42. e466c9f Re-design bakery lock memory allocation and algorithm by Andrew Thoelke · Thu Sep 10 11:39:36 2015 +0100
  43. 3700a92 PSCI: Migrate TF to the new platform API and CM helpers by Soby Mathew · Mon Jul 13 11:21:11 2015 +0100
  44. 981487a PSCI: Switch to the new PSCI frameworks by Soby Mathew · Mon Jul 13 14:10:57 2015 +0100
  45. b0082d2 PSCI: Introduce new platform and CM helper APIs by Soby Mathew · Thu Apr 09 13:40:55 2015 +0100
  46. 9ccbc03 Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1 by danh-arm · Wed Jun 24 11:23:33 2015 +0100
  47. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · Tue Jun 02 17:19:43 2015 +0100
  48. acde8b0 Rationalize reset handling code by Sandrine Bailleux · Tue May 19 11:54:45 2015 +0100
  49. 979992e Fix handling of spurious interrupts in BL3_1 by Achin Gupta · Wed May 13 17:57:18 2015 +0100
  50. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · Tue Mar 24 14:03:57 2015 +0000
  51. 00f58f0 Merge pull request #268 from vikramkanigiri/vk/move_init_cpu_ops by danh-arm · Tue Mar 17 14:23:46 2015 +0000
  52. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  53. 8723adf Enable type-checking of arguments passed to printf() et al. by Sandrine Bailleux · Thu Feb 05 15:42:31 2015 +0000
  54. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  55. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  56. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · Thu Jan 08 18:02:44 2015 +0000
  57. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · Thu Jan 08 18:02:19 2015 +0000
  58. 070a3e0 Merge pull request #206 from soby-mathew/sm/reset_cntvoff by Andrew Thoelke · Fri Oct 10 12:13:48 2014 +0100
  59. fd8c077 Fix LENGTH attribute value in linker scripts by Juan Castillo · Tue Sep 16 10:40:35 2014 +0100
  60. c93c9df Initialize SCTLR_EL1 based on MODE_RW bit by Jens Wiklander · Thu Sep 04 10:23:27 2014 +0200
  61. feddfcf Reset CNTVOFF_EL2 register before exit into EL1 on warm boot by Soby Mathew · Fri Aug 29 14:41:58 2014 +0100
  62. 046cd3f Miscellaneous documentation fixes by Sandrine Bailleux · Wed Aug 06 11:27:23 2014 +0100
  63. 38b4bc9 Add CPU specific crash reporting handlers by Soby Mathew · Thu Aug 14 13:36:41 2014 +0100
  64. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  65. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100
  66. 4dc4a47 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · Tue Aug 12 11:17:06 2014 +0100
  67. 9e46188 Merge pull request #189 from achingupta/ag/tf-issues#153 by Dan Handley · Tue Aug 19 11:04:21 2014 +0100
  68. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · Mon Aug 04 23:13:10 2014 +0100
  69. 71ac11f Merge pull request #184 from jcastillo-arm/jc/tf-issues/100 by danh-arm · Thu Aug 14 09:52:22 2014 +0100
  70. 91b624e Rationalize console log output by Dan Handley · Tue Jul 29 17:14:00 2014 +0100
  71. 0c70c57 FVP: apply new naming conventions to memory regions by Juan Castillo · Tue Aug 12 13:04:43 2014 +0100
  72. 534ae7f Merge pull request #179 from jcastillo-arm/jc/tf-issues/219 by danh-arm · Mon Aug 04 10:34:18 2014 +0100
  73. 6dc22e3 Merge pull request #178 from soby-mathew/sm/optmize_el3_context by danh-arm · Mon Aug 04 10:31:54 2014 +0100
  74. 4e81341 Support asynchronous method for BL3-2 initialization by Vikram Kanigiri · Tue Jul 15 16:49:22 2014 +0100
  75. b3dbeb0 Call platform_is_primary_cpu() only from reset handler by Juan Castillo · Wed Jul 16 15:53:43 2014 +0100
  76. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · Fri Jul 04 16:02:26 2014 +0100
  77. 5cd545d Merge pull request #177 from jcastillo-arm/jc/tf-issues/096 by danh-arm · Mon Jul 28 14:33:44 2014 +0100
  78. 45c31c4 Merge pull request #172 from soby-mathew/sm/asm_assert by danh-arm · Mon Jul 28 14:28:40 2014 +0100
  79. 3299181 Merge pull request #170 from achingupta/ag/tf-issues#226 by danh-arm · Mon Jul 28 14:27:25 2014 +0100
  80. 289162c Merge pull request #169 from achingupta/ag/tf-issues#198 by danh-arm · Mon Jul 28 14:24:52 2014 +0100
  81. f558cac Rework incorrect use of assert() and panic() in codebase by Juan Castillo · Thu Jun 05 09:45:36 2014 +0100
  82. 0da9593 Add CPUECTLR_EL1 and Snoop Control register to crash reporting by Soby Mathew · Wed Jul 16 09:23:52 2014 +0100
  83. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · Wed Jun 25 10:07:40 2014 +0100
  84. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · Fri Jul 18 18:38:28 2014 +0100
  85. 04be3a5 Add support for printing version at runtime by Juan Castillo · Mon Jun 30 11:41:46 2014 +0100
  86. afe7e2f Implement a leaner printf for Trusted Firmware by Soby Mathew · Thu Jun 12 17:23:58 2014 +0100
  87. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · Thu Jun 26 09:58:52 2014 +0100
  88. f4a9709 Remove coherent stack usage from the cold boot path by Achin Gupta · Wed Jun 25 19:26:22 2014 +0100
  89. 47a6483 Merge pull request #162 from jcastillo-arm/jc/tf-issues/194 by danh-arm · Fri Jul 11 14:17:05 2014 +0100
  90. 3c449d7 Merge pull request #163 from sandrine-bailleux/sb/tf-issue-117-v2 by danh-arm · Fri Jul 11 11:19:27 2014 +0100
  91. e2e0c65 fvp: Reuse BL1 and BL2 memory through image overlaying by Sandrine Bailleux · Mon Jun 16 16:12:27 2014 +0100
  92. 258e94f Allow FP register context to be optional at build time by Juan Castillo · Wed Jun 25 17:26:36 2014 +0100
  93. f268c72 Merge pull request #151 from vikramkanigiri/vk/t133-code-readability by Andrew Thoelke · Fri Jun 27 14:10:04 2014 +0100
  94. 2d55240 Remove all checkpatch errors from codebase by Juan Castillo · Fri Jun 13 17:05:10 2014 +0100
  95. cf79bf5 Simplify entry point information generation code on FVP by Vikram Kanigiri · Mon Jun 02 14:59:00 2014 +0100
  96. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  97. 40110f7 Merge pull request #138 from athoelke/at/cpu-context by danh-arm · Mon Jun 23 13:10:00 2014 +0100
  98. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · Mon Jun 02 12:38:12 2014 +0100
  99. c02dbd6 Move CPU context pointers into cpu_data by Andrew Thoelke · Mon Jun 02 10:00:25 2014 +0100
  100. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100