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git01.mediatek.com / filogic / atf / 65bc9b327568b5b4dd7a5142c385575d32e988b1 / plat / renesas / rcar / plat_pm.c
  1. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  2. b67a8ca rcar_gen3: drivers: Change to restore timer counter value at resume by Toshiyuki Ogasahara · Fri Mar 22 16:14:00 2019 +0900
  3. 4ae342c rcar_gen3: plat: Add initial D3 support by Marek Vasut · Sat Jan 05 13:56:03 2019 +0100
  4. 122555f rcar_gen3: plat: Add missing cpu_on_check() implementation by Marek Vasut · Sat Jan 05 16:21:14 2019 +0100
  5. 38ec9e5 rcar_gen3: drivers: cpld: Move rcar_cpld_reset_cpu() into header by Marek Vasut · Fri Dec 28 11:26:03 2018 +0100
  6. e724649 rcar_gen3: plat: Clean up rcar_pwrc_code_copy_to_system_ram() by Marek Vasut · Mon Dec 31 17:12:45 2018 +0100
  7. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  8. bf084dc rcar-gen3: initial commit for the rcar-gen3 boards by Jorge Ramirez-Ortiz · Sun Sep 23 09:36:13 2018 +0200