- 890e02b chore: use tabs for indentation by Jorge Troncoso · 2 years, 3 months ago
- 2f2b61c fix(intel): remove unused printout by Sieu Mun Tang · 2 years, 6 months ago
- c366760 fix(intel): fix configuration status based on start request by Sieu Mun Tang · 2 years, 6 months ago
- 4f5554c style(intel): align the sequence in header file by Sieu Mun Tang · 2 years, 6 months ago
- 7420c53 fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD by Sieu Mun Tang · 2 years, 6 months ago
- 527df9f fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying by Sieu Mun Tang · 2 years, 7 months ago
- e77d37d fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying by Sieu Mun Tang · 2 years, 7 months ago
- 9bea815 fix(intel): extending to support large file size for AES encryption and decryption by Sieu Mun Tang · 2 years, 7 months ago
- 5d187c0 feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands by Sieu Mun Tang · 2 years, 6 months ago
- 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years, 6 months ago
- d2df204 fix(intel): update certificate mask for FPGA Attestation by Boon Khai Ng · 3 years, 3 months ago
- 758a2ad feat(intel): update to support maximum response data size by Sieu Mun Tang · 2 years, 6 months ago
- 59357e8 feat(intel): support ECDSA HASH Verification by Sieu Mun Tang · 2 years, 6 months ago
- 8aa05ad feat(intel): support ECDSA HASH Signing by Sieu Mun Tang · 2 years, 6 months ago
- 0675c22 feat(intel): support ECDH request by Sieu Mun Tang · 2 years, 6 months ago
- dcaab77 feat(intel): support ECDSA SHA-2 Data Signature Verification by Sieu Mun Tang · 2 years, 6 months ago
- 153ecfb feat(intel): support ECDSA SHA-2 Data Signing by Sieu Mun Tang · 2 years, 6 months ago
- e2f3ede feat(intel): support ECDSA Get Public Key by Sieu Mun Tang · 2 years, 6 months ago
- 22322fb feat(intel): support session based SDOS encrypt and decrypt by Sieu Mun Tang · 2 years, 6 months ago
- b0c1d11 feat(intel): support AES Crypt Service by Sieu Mun Tang · 2 years, 6 months ago
- 583149a feat(intel): support HMAC SHA-2 MAC verify request by Sieu Mun Tang · 2 years, 6 months ago
- d907cc3 feat(intel): support SHA-2 hash digest generation on a blob by Sieu Mun Tang · 2 years, 6 months ago
- e7a037f feat(intel): support extended random number generation by Sieu Mun Tang · 2 years, 6 months ago
- fb1f6e9 feat(intel): support crypto service key operation by Sieu Mun Tang · 2 years, 6 months ago
- 16754e1 feat(intel): support crypto service session by Sieu Mun Tang · 2 years, 6 months ago
- 28af165 feat(intel): extend attestation service to Agilex family by Sieu Mun Tang · 2 years, 6 months ago
- cac786d fix(intel): flush dcache before sending certificate to mailbox by Boon Khai Ng · 3 years, 6 months ago
- 96bbdca fix(intel): introduce a generic response error code by Sieu Mun Tang · 2 years, 7 months ago
- fd8a8ad fix(intel): allow non-secure access to FPGA Crypto Services (FCS) by Sieu Mun Tang · 2 years, 7 months ago
- a068fdf feat(intel): single certificate feature enablement by Sieu Mun Tang · 2 years, 6 months ago
- 2a820b9 feat(intel): initial commit for attestation service by Sieu Mun Tang · 2 years, 6 months ago
- 128d2a7 fix(intel): update encryption and decryption command logic by Sieu Mun Tang · 2 years, 6 months ago
- 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years, 6 months ago
- a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 8 months ago
- 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years, 7 months ago
- db79fa5 fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS) by Sieu Mun Tang · 2 years, 8 months ago
- e768dfa feat(intel): add SMC support for HWMON voltage and temp sensor by Kris Chaplin · 3 years, 5 months ago
- 2b8e005 feat(intel): add SMC support for Get USERCODE by Sieu Mun Tang · 2 years, 7 months ago
- bfda95a fix(intel): extend SDM command to return the SDM firmware version by Sieu Mun Tang · 2 years, 7 months ago
- d9006fc feat(intel): add SMC for enquiring firmware version by Abdul Halim, Muhammad Hadi Asyrafi · 3 years, 10 months ago
- 959143d fix(intel): configuration status based on start request by Abdul Halim, Muhammad Hadi Asyrafi · 3 years, 11 months ago
- 5406498 fix(intel): bit-wise configuration flag handling by Sieu Mun Tang · 2 years, 7 months ago
- 37c7076 fix(intel): get config status OK status by Abdul Halim, Muhammad Hadi Asyrafi · 4 years ago
- fbc3913 fix(intel): use macro as return value by Abdul Halim, Muhammad Hadi Asyrafi · 4 years ago
- 351e884 fix(intel): fix fpga config write return mechanism by Abdul Halim, Muhammad Hadi Asyrafi · 4 years ago
- e6d5de9 feat(intel): add SiP service for DCMF status by Sieu Mun Tang · 2 years, 7 months ago
- 681631b feat(intel): add RSU 'Max Retry' SiP SMC services by Chee Hong Ang · 4 years, 5 months ago
- b30ce3f feat(intel): enable SMC SoC FPGA bridges enable/disable by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 5 months ago
- 2cfd8ec feat(intel): add SMC/PSCI services for DCMF version support by Chee Hong Ang · 4 years, 6 months ago
- 869d4f5 feat(intel): allow to access all register addresses if DEBUG=1 by Siew Chin Lim · 3 years, 6 months ago
- b251c33 fix(intel): modify how configuration type is handled by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- f9cb657 feat(intel): support SiP SVC version by Sieu Mun Tang · 2 years, 7 months ago
- 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 4 months ago
- 1205ef0 feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
- 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 4 months ago
- b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 3 years, 4 months ago
- a34b881 feat(intel): add SMC support for ROM Patch SHA384 mailbox by Sieu Mun Tang · 2 years, 8 months ago
- 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 3 years, 6 months ago
- a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 9 months ago
- dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 9 months ago
- f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 5 months ago
- 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 9 months ago
- 9f22cbf build(intel): initial commit for crypto driver by Sieu Mun Tang · 2 years, 9 months ago
- f57b5cc Merge changes I75b3e3bf,I4cf9f1d9,I50d2ae74,Idbe62410,I84bbd06e, ... into integration by Madhukar Pappireddy · 2 years, 9 months ago
- 2468266 fix(intel): null pointer handling for resp_len by Sieu Mun Tang · 2 years, 9 months ago
- 33b89d5 fix(intel): define macros to handle buffer entries by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- f02f0cb fix(intel): change SMC return arguments for INTEL_SIP_SMC_MBOX_SEND_CMD by Sieu Mun Tang · 2 years, 9 months ago
- bf90984 fix(intel): always set doorbell to SDM after sending command by Siew Chin Lim · 3 years, 4 months ago
- a076315 fix(intel): fix bit masking issue in intel_secure_reg_update by Siew Chin Lim · 3 years, 4 months ago
- 461f544 fix(intel): fix ddr address range checker by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 5 months ago
- ae4cd3a fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 1 month ago
- 118ab21 intel: common: Fix non-MISRA compliant code v2 by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 1 month ago
- 1b0e8cb intel: mailbox: Fix non-MISRA compliant code by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
- 5bc87bc intel: mailbox: Mailbox error recovery handling by Chee Hong Ang · 4 years, 6 months ago
- 7d66e14 intel: mailbox: Enable sending large mailbox command by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- 14a1d43 intel: mailbox: Use retry count in mailbox poll by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · 4 years, 6 months ago
- 39d137b intel: mailbox: Read mailbox response even there is an error by Chee Hong Ang · 4 years, 6 months ago
- 94fae38 intel: mailbox: Driver now handles larger response by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 7 months ago
- 20a07f3 intel: common: Change how mailbox handles job id & buffer by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- 046e1f1 intel: common: Improve readability of mailbox read response by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 9 months ago
- 99b5e16 intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB by Richard Gong · 4 years, 7 months ago
- 2b7d13e intel: common: Remove urgent from mailbox async by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- b45f15e intel: common: Improve mailbox driver readability by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- ec164b6 intel: common: Clean up mailbox and sip header by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 6 months ago
- 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · 4 years, 7 months ago
- 64d2b2f plat: intel: Additional instruction required to enable global timer by Tien Hock Loh · 4 years, 6 months ago
- 070ffbb plat: intel: Fix CCU initialization for Agilex by Tien Hock Loh · 4 years, 6 months ago
- c5baddf plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · 4 years, 6 months ago
- fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 4 years, 6 months ago
- 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · 4 years, 9 months ago
- 6bedfe2 Merge "intel: Fix argument type for mailbox driver" into integration by Sandrine Bailleux · 4 years, 9 months ago
- 25f623e intel: Update RSU driver return code by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 9 months ago
- d84bfef intel: Fix argument type for mailbox driver by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 9 months ago
- 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · 5 years ago
- c4c4dec Merge "intel: Fix Coverity Scan Defects" into integration by Sandrine Bailleux · 4 years, 9 months ago
- e59b999 intel: Fix Coverity Scan Defects by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 9 months ago
- 7f95059 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · 4 years, 9 months ago
- c39a0e0 intel: Include address range check for SiP Mailbox by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 10 months ago
- a33e810 intel: Introduce SMC support for mailbox command by Hadi Asyrafi · 5 years ago