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git01.mediatek.com / filogic / atf / 5e79cfe49420aadc44e07e53a95df642b083e64b / include / bl31 / interrupt_mgmt.h
  1. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  2. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  3. e0b757d Fix MISRA defects in BL31 common code by Antonio Nino Diaz · Fri Aug 24 16:30:29 2018 +0100
  4. 837cc9c EHF: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  5. 32ceef5 SDEI: MISRA fixes by Jeenu Viswambharan · Thu Aug 02 10:14:12 2018 +0100
  6. 777dd43 Fix MISRA rule 8.3 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  7. f4194ee Deprecate one EL3 interrupt routing model with EL3 exception handling by Jeenu Viswambharan · Wed Jan 10 15:00:20 2018 +0000
  8. aeb267c GIC: Allow specifying interrupt properties by Jeenu Viswambharan · Fri Sep 22 08:32:09 2017 +0100
  9. dce70b3 GIC: Add API to set interrupt routing by Jeenu Viswambharan · Fri Sep 22 08:32:09 2017 +0100
  10. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  11. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  12. 58e32d1 Enable support for EL3 interrupt in IMF by Soby Mathew · Mon Nov 23 13:58:45 2015 +0000
  13. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  14. a17fefa Remove extern keyword from function declarations by Dan Handley · Wed May 14 12:38:32 2014 +0100
  15. 191e86e Introduce interrupt registration framework in BL3-1 by Achin Gupta · Fri May 09 10:03:15 2014 +0100