Log - 574d68535b788ee455898b3c99cac00623942c92 - filogic/atf

d1b6150 Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs by Varun Wadekar · Thu Jul 16 09:46:28 2015 +0530
6cab707 Tegra210: lock PMC registers holding CPU vector addresses by Varun Wadekar · Thu Jul 16 11:58:19 2015 +0530
071b787 Tegra210: deassert CPU reset signals during power on by Varun Wadekar · Wed Jul 08 17:42:02 2015 +0530
81b1383 Implement get_sys_suspend_power_state() handler for Tegra by Varun Wadekar · Fri Jul 03 16:31:28 2015 +0530
b316e24 Support for NVIDIA's Tegra T210 SoCs by Varun Wadekar · Tue May 19 16:48:04 2015 +0530