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git01.mediatek.com / filogic / atf / 506da9307ea9bb79d86f97fb6d6da9b5a651af58 / plat / intel / soc / n5x / include
  1. 7a22863 Merge changes Id85b2541,I4d253e2f into integration by Sandrine Bailleux · Wed Jan 10 13:54:11 2024 +0100
  2. 6e0e1b5 fix(intel): update system counter back to 400MHz by Sieu Mun Tang · Fri Dec 22 11:30:46 2023 +0800
  3. fe91ca3 feat(intel): support QSPI ECC Linux for N5X by Jit Loon Lim · Wed Oct 18 16:19:18 2023 +0800
  4. e7ab132 Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration by Sandrine Bailleux · Tue Dec 19 16:12:59 2023 +0100
  5. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · Fri Jul 07 17:15:26 2023 +0800
  6. 6284537 feat(intel): restructure watchdog by Sieu Mun Tang · Fri Jun 09 23:33:36 2023 +0800
  7. 4c249f1 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  8. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  9. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · Thu Dec 22 21:52:36 2022 +0800
  10. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · Thu Jun 23 18:05:02 2022 +0800
  11. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  12. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  13. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  14. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  15. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · Mon Mar 07 12:04:59 2022 +0800