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filogic
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atf
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4d1610baadcce0c63ea140e1940982d65c8cc74f
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lib
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cpus
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aarch64
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cortex_a72.S
caa2e05
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
by Bipin Ravi
· 2 years, 7 months ago
cf4d50a
fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72
by Bipin Ravi
· 2 years, 7 months ago
7672edf
lib/cpus: Report AT speculative erratum workaround
by Manish V Badarkhe
· 4 years, 2 months ago
bb0aa39
cpulib: Add ISBs or comment why they are unneeded
by Dimitris Papastamos
· 6 years ago
ba51d9e
Add support for dynamic mitigation for CVE-2018-3639
by Dimitris Papastamos
· 6 years ago
e6625ec
Implement static workaround for CVE-2018-3639
by Dimitris Papastamos
· 6 years ago
570c06a
Rename symbols and files relating to CVE-2017-5715
by Dimitris Papastamos
· 6 years ago
914757c
Fixup `SMCCC_ARCH_FEATURES` semantics
by Dimitris Papastamos
· 7 years ago
780cc95
Use PFR0 to identify need for mitigation of CVE-2017-5715
by Dimitris Papastamos
· 7 years ago
858bd61
Print erratum application report for CVE-2017-5715
by Dimitris Papastamos
· 7 years ago
446f7f1
Workaround for CVE-2017-5715 on Cortex A57 and A72
by Dimitris Papastamos
· 7 years ago
c3b4ca1
Cortex-A72: Implement workaround for erratum 859971
by Eleanor Bonnici
· 7 years ago
41b61be
CPU: Correct names of implementation-defined aux regs
by Eleanor Bonnici
· 7 years ago
1384a16
Unique names for defines in the CPU libraries
by Varun Wadekar
· 7 years ago
fa3cf0b
Use SPDX license identifiers
by dp-arm
· 7 years ago
ee5eb80
Add provision to extend CPU operations at more levels
by Jeenu Viswambharan
· 8 years ago
6a72a91
bl31: Add error reporting registers
by Naga Sureshkumar Relli
· 8 years ago
a877c25
Add support to indicate size and end of assembly functions
by Kévin Petit
· 9 years ago
c47e011
Add support for ARM Cortex-A72 processor
by Vikram Kanigiri
· 10 years ago