Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 4abeb0e2f99b78b7d32074d9791701e8546b98ea / plat / xilinx / zynqmp / include / platform_def.h
  1. e748f9f fix(zynqmp): type cast addresses to fix overflow issue by Akshay Belsare · Thu Jun 08 11:19:54 2023 +0530
  2. bd54123 fix(zynqmp): fix BLXX memory limits for user defined values by Ilias Apalodimas · Thu May 18 12:05:43 2023 +0300
  3. 2078cb9 Merge "fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS" into integration by Joanna Farley · Thu Apr 20 10:19:41 2023 +0200
  4. ffe7c68 fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS by Michal Simek · Mon Apr 17 13:51:59 2023 +0200
  5. 2a47faa style(xilinx): replace ARM by Arm in copyrights by Michal Simek · Fri Apr 14 08:43:51 2023 +0200
  6. 32d5c90 feat(zynqmp): make stack size configurable by Akshay Belsare · Thu Apr 06 16:21:06 2023 +0530
  7. ec0afc8 fix(zynqmp): conditional reservation of memory in DTB by Akshay Belsare · Mon Feb 27 12:04:26 2023 +0530
  8. 71e1ffc feat(zynqmp): add hooks for mmap and early setup by Amit Nagal · Thu Feb 23 21:37:23 2023 +0530
  9. 69c6a59 fix(zynqmp): with DEBUG=1 move bl31 to DDR range by Akshay Belsare · Wed Feb 15 10:49:52 2023 +0530
  10. b7a57b5 fix(zynqmp): update MAX_XLAT_TABLES for DDR memory range by Akshay Belsare · Wed Feb 15 17:29:42 2023 +0530
  11. 19334d0 fix(zynqmp): move debug bl31 based address back to OCM by Michal Simek · Thu Aug 04 09:18:06 2022 +0200
  12. dfbb093 fix(zynqmp): move bl31 with DEBUG=1 back to OCM by Michal Simek · Wed Jun 15 14:19:56 2022 +0200
  13. ed4f1e8 fix(zynqmp): resolve misra 7.2 warnings by Venkatesh Yadav Abbarapu · Fri Apr 29 09:58:30 2022 +0530
  14. 586e192 feat(zynqmp): increase the max xlat tables when debug build is enabled by Venkatesh Yadav Abbarapu · Tue Mar 01 22:10:05 2022 -0700
  15. ed22a34 feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM' by Giulio Benetti · Sat Feb 05 09:42:29 2022 +0100
  16. 53865b0 feat(plat/zynqmp): extend DT description by TF-A by Michal Simek · Thu May 27 09:42:37 2021 +0200
  17. e1407fc feat(plat/zynqmp): add SDEI support by Jan Kiszka · Tue Jul 14 22:36:59 2020 +0200
  18. b16bada xilinx: Unify Platform specific defines for PSCI module by Deepika Bhavnani · Fri Dec 13 10:53:56 2019 -0600
  19. afa91db Arm platforms: Rename PLAT_ARM_NS_IMAGE_OFFSET by Sandrine Bailleux · Thu Jan 31 15:01:32 2019 +0100
  20. 16fe5ab plat: xilinx: zynqmp: Move zynqmp_def.h to include directory by Jolly Shah · Tue Jan 08 11:16:16 2019 -0800
  21. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  22. 6f3ccc5 PSCI: Fix types of definitions by Antonio Nino Diaz · Fri Jul 20 09:17:26 2018 +0100
  23. ee1a114 plat: xilinx: zynqmp: Build for DDR if SPD is enabled by Siva Durga Prasad Paladugu · Wed Jun 20 17:01:13 2018 +0530
  24. efd431b zynqmp: Add wdt timeout restart functionality by Siva Durga Prasad Paladugu · Mon Apr 30 20:12:12 2018 +0530
  25. 8f5ddb3 zynqmp: Use DDR memory when DEBUG is enabled by Jolly Shah · Tue Jan 30 11:31:53 2018 -0800
  26. c150312 Update ULL() macro and instances of ull to comply with MISRA by David Cunado · Fri Feb 16 21:12:58 2018 +0000
  27. 9bde130 zynqmp: Migrate to using interrupt properties by Jeenu Viswambharan · Fri Sep 29 11:15:18 2017 +0100
  28. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  29. 6a9e03e zynqmp: Migrate to new address space macros by Soren Brinkmann · Fri Jan 06 11:07:00 2017 -0800
  30. 1209b26 zynqmp: Remove dead code by Soren Brinkmann · Wed Nov 16 15:50:14 2016 -0800
  31. 7ac746c zynqmp: Increase MAX_XLAT_TABLES by Soren Brinkmann · Mon Jul 25 10:33:53 2016 -0700
  32. 802ba1d zynqmp: Change default BL31 address space by Soren Brinkmann · Fri Jul 15 06:23:37 2016 -0700
  33. 6d1ba58 zynqmp: Separate code and rodata by Soren Brinkmann · Fri Jul 08 14:45:14 2016 -0700
  34. 845cd5c zynqmp: Reduce mapped memory area by Soren Brinkmann · Fri Apr 22 10:02:46 2016 -0700
  35. 4a9ca04 zynqmp: Revise memory configuration options by Soren Brinkmann · Thu Apr 14 10:27:00 2016 -0700
  36. 76fcae3 Add support for Xilinx Zynq UltraScale+ MPSOC by Soren Brinkmann · Sun Mar 06 20:16:27 2016 -0800