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git01.mediatek.com / filogic / atf / 47a90643772c41260078056f631419aa0d297685 / lib / cpus
  1. 16e6d9f Rename Cortex-Helios to Neoverse E1 by John Tsichritzis · Tue Feb 19 14:01:55 2019 +0000
  2. 3d417ac Rename Cortex-Helios filenames to Neoverse E1 by John Tsichritzis · Tue Feb 19 13:54:21 2019 +0000
  3. 56369c1 Rename Cortex-Ares to Neoverse N1 by John Tsichritzis · Tue Feb 19 13:49:06 2019 +0000
  4. 97ff6d0 Rename Cortex-Ares filenames to Neoverse N1 by John Tsichritzis · Tue Feb 19 13:48:44 2019 +0000
  5. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  6. aa00aff AArch64: Use SSBS for CVE_2018_3639 mitigation by Jeenu Viswambharan · Thu Nov 15 11:38:03 2018 +0000
  7. 9fe40fd Fix MISRA defects in workaround and errata framework by Antonio Nino Diaz · Thu Oct 25 17:11:02 2018 +0100
  8. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  9. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  10. 7c461d7 ti: k3: common: Do not disable cache on TI K3 core powerdown by Andrew F. Davis · Fri Oct 12 15:37:04 2018 -0500
  11. 5e7e4a7 Fix the Cortex-ares errata reporting function name by Soby Mathew · Mon Sep 10 11:14:01 2018 +0100
  12. cd38e6e cpus: denver: Implement static workaround for CVE-2018-3639 by Varun Wadekar · Tue Aug 28 09:11:30 2018 -0700
  13. 2b91412 cpus: denver: reset power state to 'C1' on boot by Varun Wadekar · Mon Jun 25 11:36:47 2018 -0700
  14. 007a206 denver: use plat_my_core_pos() to get core position by Varun Wadekar · Tue Feb 27 18:30:31 2018 -0800
  15. 13110b4 DSU erratum 936184 workaround: bug fix by John Tsichritzis · Wed Aug 22 10:40:33 2018 +0100
  16. 268e699 Merge pull request #1388 from vwadekar/report-cve-2017-5715 by Dimitris Papastamos · Mon Aug 20 14:57:39 2018 +0100
  17. bc242fa cpus: denver: report CVE_2017_5715 mitigation to higher layers by Varun Wadekar · Fri Jul 06 13:39:52 2018 -0700
  18. 4daa1de DSU erratum 936184 workaround by John Tsichritzis · Mon Jul 23 09:11:59 2018 +0100
  19. a7c4687 Add initial CPU support for Cortex-Helios by Joel Hutton · Wed Jan 10 16:06:07 2018 +0000
  20. 9463cae Add initial CPU support for Cortex-Deimos by Joel Hutton · Fri May 04 15:09:47 2018 +0100
  21. 95f30ab Add end_vector_entry assembler macro by Roberto Vargas · Tue Apr 17 11:31:43 2018 +0100
  22. bb0aa39 cpulib: Add ISBs or comment why they are unneeded by Dimitris Papastamos · Thu Jun 07 13:20:19 2018 +0100
  23. 14f7005 Fix MISRA Rule 5.7 Part 1 by Daniel Boulby · Thu May 03 10:59:09 2018 +0100
  24. 8c18f6a Merge pull request #1397 from dp-arm/dp/cortex-a76 by Dimitris Papastamos · Fri Jun 08 14:01:38 2018 +0100
  25. 312e17e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 by Dimitris Papastamos · Wed May 16 09:59:54 2018 +0100
  26. 7ca21db Implement Cortex-Ares 1043202 erratum workaround by Dimitris Papastamos · Mon Mar 26 16:46:01 2018 +0100
  27. 89736dd Add AMU support for Cortex-Ares by Dimitris Papastamos · Tue Feb 13 11:28:02 2018 +0000
  28. ea84d6b Add support for Cortex-Ares and Cortex-A76 CPUs by Isla Mitchell · Thu Aug 03 16:04:46 2017 +0100
  29. 6694633 Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32 by Dimitris Papastamos · Thu May 31 11:38:33 2018 +0100
  30. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  31. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  32. e6625ec Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu Apr 05 14:38:26 2018 +0100
  33. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · Fri Apr 06 15:29:34 2018 +0100
  34. e34bd09 Workaround for CVE-2017-5715 on NVIDIA Denver CPUs by Varun Wadekar · Wed Jan 10 17:03:22 2018 -0800
  35. 6e1796e Check presence of fix for errata 835769 in Cortex-A53 by Jonathan Wright · Wed Mar 28 16:55:54 2018 +0100
  36. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  37. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  38. 780cc95 Use PFR0 to identify need for mitigation of CVE-2017-5715 by Dimitris Papastamos · Mon Mar 12 13:27:02 2018 +0000
  39. 864364a MISRA fixes for Cortex A75 AMU implementation by Dimitris Papastamos · Tue Feb 27 10:55:39 2018 +0000
  40. 1be747f Refactor AMU support for Cortex A75 by Dimitris Papastamos · Wed Feb 14 10:28:36 2018 +0000
  41. 0b00f8a Factor out CPU AMU helpers by Dimitris Papastamos · Wed Feb 14 10:00:06 2018 +0000
  42. d1e1930 Fixup AArch32 errata printing framework by Soby Mathew · Wed Feb 21 15:48:03 2018 +0000
  43. 8ca3144 Merge pull request #1253 from dp-arm/dp/amu32 by davidcunado-arm · Fri Feb 02 11:14:17 2018 +0000
  44. 0dcdd8d AMU: Implement context save/restore for aarch32 by Joel Hutton · Thu Dec 21 15:21:20 2017 +0000
  45. 2880363 Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 by Dimitris Papastamos · Mon Jan 08 13:57:39 2018 +0000
  46. b63c6f1 Optimize/cleanup BPIALL workaround by Dimitris Papastamos · Thu Jan 11 15:29:36 2018 +0000
  47. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  48. 471fb9b Merge pull request #1229 from manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix by davidcunado-arm · Sat Jan 20 17:04:49 2018 +0000
  49. b5d1f8e Merge pull request #1200 from robertovargas-arm/bl2-el3 by davidcunado-arm · Fri Jan 19 13:40:12 2018 +0000
  50. e37c029 lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode by Manoj Kumar · Fri Jan 19 17:51:31 2018 +0530
  51. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  52. 858bd61 Print erratum application report for CVE-2017-5715 by Dimitris Papastamos · Tue Jan 16 10:32:47 2018 +0000
  53. 84e02dc Change the default errata format string by Dimitris Papastamos · Tue Jan 16 10:42:20 2018 +0000
  54. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  55. fa2b736 Merge pull request #1197 from dp-arm/dp/amu by davidcunado-arm · Fri Jan 12 09:02:24 2018 +0000
  56. d7e2e9e Add hooks to save/restore AMU context for Cortex A75 by Dimitris Papastamos · Mon Dec 11 11:45:35 2017 +0000
  57. 43e05ec Use PFR0 to identify need for mitigation of CVE-2017-5915 by Dimitris Papastamos · Tue Jan 02 15:53:01 2018 +0000
  58. c52ebdc Workaround for CVE-2017-5715 on Cortex A73 and A75 by Dimitris Papastamos · Mon Dec 18 13:46:21 2017 +0000
  59. 446f7f1 Workaround for CVE-2017-5715 on Cortex A57 and A72 by Dimitris Papastamos · Thu Nov 30 14:53:53 2017 +0000
  60. 4c24bb7 Merge pull request #1168 from matt2048/master by davidcunado-arm · Mon Dec 04 22:39:40 2017 +0000
  61. fcedb69 Implement support for the Activity Monitor Unit on Cortex A75 by Dimitris Papastamos · Mon Oct 16 11:40:10 2017 +0100
  62. 41b0094 Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS by Matt Ma · Wed Nov 22 19:31:28 2017 +0800
  63. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  64. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  65. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  66. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  67. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  68. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  69. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  70. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  71. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  72. 9930501 Fix order of #includes by Isla Mitchell · Tue Jul 11 14:54:08 2017 +0100
  73. d0c8273 Introduce TF_LDFLAGS by Douglas Raillard · Thu Jun 22 14:44:48 2017 +0100
  74. 505f467 Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53 by danh-arm · Wed Jun 28 13:47:40 2017 +0100
  75. 8a354f1 Resolve signed-unsigned comparison issues by David Cunado · Wed Jun 21 16:52:45 2017 +0100
  76. d56fb04 Apply workarounds for A53 Cat A Errata 835769 and 843419 by Douglas Raillard · Mon Jun 19 15:38:02 2017 +0100
  77. 2b40ca6 aarch32: Implement errata workarounds for Cortex A57 by Dimitris Papastamos · Mon Jun 05 14:55:41 2017 +0100
  78. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  79. 370542e aarch32: Implement cpu_rev_var_hs() by Dimitris Papastamos · Mon Jun 05 13:36:34 2017 +0100
  80. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  81. 66231d1 Tegra: enable 'signed-comparison' compilation warning/errors by Varun Wadekar · Wed Jun 07 09:57:42 2017 -0700
  82. 805c2c7 Add support for Cortex-A75 and Cortex-A55 CPUs by David Wang · Wed Nov 09 16:29:02 2016 +0000
  83. 815faa8 Use a callee-saved register to be AAPCS-compliant by dp-arm · Fri May 05 12:21:03 2017 +0100
  84. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  85. bf360df Merge pull request #910 from dp-arm/dp/AArch32-juno-port by davidcunado-arm · Fri Apr 21 17:10:27 2017 +0100
  86. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  87. 7c65c1e Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · Thu Apr 20 09:58:28 2017 +0100
  88. 8cbdab2 Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test by davidcunado-arm · Wed Mar 29 09:58:20 2017 +0100
  89. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · Thu Oct 06 16:54:53 2016 +0100
  90. 9d92e8c Replace ASM signed tests with unsigned by Douglas Raillard · Tue Mar 07 16:36:14 2017 +0000
  91. c4364f6 Merge pull request #856 from antonio-nino-diaz-arm/an/dynamic-xlat by davidcunado-arm · Thu Mar 16 12:42:32 2017 +0000
  92. 3f13c35 Apply workaround for errata 813419 of Cortex-A57 by Antonio Nino Diaz · Fri Feb 24 11:39:22 2017 +0000
  93. 0a7e27c Merge pull request #853 from vwadekar/tegra-changes-from-downstream-v3 by davidcunado-arm · Thu Mar 02 15:27:33 2017 +0000
  94. 8f87cc3 cpus: denver: remove barrier from denver_enable_dco() by Varun Wadekar · Fri May 06 16:35:30 2016 -0700
  95. 1cc176b Merge pull request #848 from douglas-raillard-arm/dr/improve_errata_doc by danh-arm · Tue Feb 28 12:07:32 2017 +0000
  96. d43583c cpus: denver: disable DCO operations from platform code by Varun Wadekar · Mon Feb 22 11:09:41 2016 -0800
  97. c847f66 Clarify errata ERRATA_A53_836870 documentation by Douglas Raillard · Wed Feb 15 17:38:43 2017 +0000
  98. 3c337a6 cpus: Add support for all Denver variants by Varun Wadekar · Thu Sep 03 17:15:06 2015 +0530
  99. d5ec367 Report errata workaround status to console by Jeenu Viswambharan · Tue Jan 03 11:01:51 2017 +0000
  100. 441bfdd Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · Sun Dec 25 23:36:24 2016 +0900