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git01.mediatek.com / filogic / atf / 3f76e138bb9d48ca5d700af6eb8b66cefd462c68 / plat / intel / soc / n5x / soc
  1. 60f7fb8 fix(intel): revert back to use L4 clock by Sieu Mun Tang · 11 months ago
  2. ffa06e7 fix(intel): fix hardcoded mpu frequency ticks by Jit Loon Lim · 1 year, 4 months ago
  3. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · 1 year, 6 months ago
  4. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 11 months ago
  5. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago