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git01.mediatek.com / filogic / atf / 3f3a922a39541b06c91a5c77ef40aac79a0b935f / include / lib / el3_runtime / cpu_data.h
  1. b6301e6 feat(rme): add context management changes for FEAT_RME by Zelalem Aweke · Fri Jul 09 17:54:30 2021 -0500
  2. f57491e fix(el3_runtime): correct CASSERT for pauth by Olivier Deprez · Thu Aug 19 11:36:26 2021 +0200
  3. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  4. 8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
  5. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  6. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  7. 864ca6f context_mgmt: Fix MISRA defects by Antonio Nino Diaz · Wed Oct 31 15:25:35 2018 +0000
  8. 9fe40fd Fix MISRA defects in workaround and errata framework by Antonio Nino Diaz · Thu Oct 25 17:11:02 2018 +0100
  9. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  10. 10a6727 BL31: Introduce Exception Handling Framework by Jeenu Viswambharan · Fri Sep 22 08:32:10 2017 +0100
  11. 43a4d57 Change sizeof to use type of struct not function by Joel Hutton · Fri Oct 20 10:31:14 2017 +0100
  12. 97ad6ce cpu log buffer size depends on cache line size by Etienne Carriere · Fri Sep 01 10:22:20 2017 +0200
  13. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  14. 3cac786 Add PMF instrumentation points in TF by dp-arm · Mon Sep 19 11:18:44 2016 +0100
  15. 748be1d AArch32: Add support in TF libraries by Soby Mathew · Thu May 05 14:10:46 2016 +0100
  16. 0d78607 Introduce `el3_runtime` and `PSCI` libraries by Soby Mathew · Thu Mar 24 16:56:29 2016 +0000[Renamed from include/bl31/cpu_data.h]
  17. 24ab34f Fix coding guideline warnings by Soby Mathew · Tue May 03 17:11:42 2016 +0100
  18. a0fedc4 Rework type usage in Trusted Firmware by Soby Mathew · Thu Jun 16 14:52:04 2016 +0100
  19. 3700a92 PSCI: Migrate TF to the new platform API and CM helpers by Soby Mathew · Mon Jul 13 11:21:11 2015 +0100
  20. 85dbf5a PSCI: Add framework to handle composite power states by Soby Mathew · Tue Apr 07 12:16:56 2015 +0100
  21. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  22. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · Thu Jan 08 18:02:19 2015 +0000
  23. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · Tue Nov 18 10:14:14 2014 +0000
  24. c704cbc Introduce framework for CPU specific operations by Soby Mathew · Thu Aug 14 11:33:56 2014 +0100
  25. f3ccbab Add PSCI service specific per-CPU data by Achin Gupta · Fri Jul 25 14:52:47 2014 +0100
  26. e4b9fa4 Add macro to flush per-CPU data by Achin Gupta · Fri Jul 25 14:47:05 2014 +0100
  27. c1adbbc Rework the crash reporting in BL3-1 to use less stack by Soby Mathew · Wed Jun 25 10:07:40 2014 +0100
  28. c02dbd6 Move CPU context pointers into cpu_data by Andrew Thoelke · Mon Jun 02 10:00:25 2014 +0100
  29. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100