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git01.mediatek.com / filogic / atf / 3a11eda2b3877aad91223db70a00ead83395abb2 / services
  1. 7866424 TSP: Allow preemption of synchronous S-EL1 interrupt handling by Soby Mathew · Fri Nov 13 02:08:43 2015 +0000
  2. bec9851 Enable use of FIQs and IRQs as TSP interrupts by Soby Mathew · Thu Sep 03 18:29:38 2015 +0100
  3. bc91282 Unify interrupt return paths from TSP into the TSPD by Soby Mathew · Tue Sep 22 12:01:18 2015 +0100
  4. c5204fa Remove the IMF_READ_INTERRUPT_ID build option by Soby Mathew · Tue Oct 27 10:01:06 2015 +0000
  5. 5e1fa05 TLKD: pass results with TLK_RESUME_FID function ID by Varun Wadekar · Wed Oct 07 17:15:41 2015 +0530
  6. d50e7d9 PSCI: Update state only if CPU_OFF is not denied by SPD by Soby Mathew · Thu Oct 01 16:46:06 2015 +0100
  7. a70dec3 Send power management events to the Trusted OS (TLK) by Varun Wadekar · Wed Aug 26 12:49:03 2015 +0530
  8. e9c4a64 Make generic code work in presence of system caches by Achin Gupta · Fri Sep 11 16:03:13 2015 +0100
  9. a31c9f3 Merge pull request #390 from vikramkanigiri/at/unify_bakery_locks_v2 by Achin Gupta · Mon Sep 14 21:49:10 2015 +0100
  10. e466c9f Re-design bakery lock memory allocation and algorithm by Andrew Thoelke · Thu Sep 10 11:39:36 2015 +0100
  11. 9a0ff9b Pass the target suspend level to SPD suspend hooks by Achin Gupta · Mon Sep 07 20:43:27 2015 +0100
  12. 3543c7b Merge pull request #361 from achingupta/for_sm/psci_proto_v5 by Achin Gupta · Mon Aug 17 14:56:31 2015 +0100
  13. 011ca18 PSCI: Rework generic code to conform to coding guidelines by Soby Mathew · Wed Jul 29 17:05:03 2015 +0100
  14. f1f97a1 PSCI: Fix the return code for invalid entrypoint by Soby Mathew · Wed Jul 15 12:13:26 2015 +0100
  15. da43b66 PSCI: Migrate SPDs and TSP to the new platform and framework API by Soby Mathew · Wed Jul 08 21:45:46 2015 +0100
  16. 981487a PSCI: Switch to the new PSCI frameworks by Soby Mathew · Mon Jul 13 14:10:57 2015 +0100
  17. 49473e4 PSCI: Implement platform compatibility layer by Soby Mathew · Wed Jun 10 13:49:59 2015 +0100
  18. 574d685 PSCI: Unify warm reset entry points by Sandrine Bailleux · Thu Jun 11 10:46:48 2015 +0100
  19. 85dbf5a PSCI: Add framework to handle composite power states by Soby Mathew · Tue Apr 07 12:16:56 2015 +0100
  20. 9d754f6 PSCI: Introduce new platform interface to describe topology by Soby Mathew · Wed Apr 08 17:42:06 2015 +0100
  21. b0082d2 PSCI: Introduce new platform and CM helper APIs by Soby Mathew · Thu Apr 09 13:40:55 2015 +0100
  22. 3a9e8bf PSCI: Remove references to affinity based power management by Soby Mathew · Tue May 05 16:33:16 2015 +0100
  23. 6b8b302 PSCI: Invoke PM hooks only for the highest level by Soby Mathew · Tue Jun 30 11:00:24 2015 +0100
  24. 991d42c PSCI: Create new directory to implement new frameworks by Soby Mathew · Mon Jun 29 16:30:12 2015 +0100
  25. f5bd697 tlkd: delete 'NEED_BL32' build variable by Varun Wadekar · Fri Jul 24 18:00:33 2015 +0530
  26. 2e0764b Merge pull request #324 from soby-mathew/sm/sys_suspend by danh-arm · Thu Jul 02 16:17:11 2015 +0100
  27. 9ccbc03 Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1 by danh-arm · Wed Jun 24 11:23:33 2015 +0100
  28. 9616838 PSCI: Add SYSTEM_SUSPEND API support by Soby Mathew · Wed Dec 17 14:47:57 2014 +0000
  29. 33e7d6a Fix integer extension in mpidr_set_aff_inst() by Andrew Thoelke · Thu Jun 11 14:22:07 2015 +0100
  30. 449dbd5 Introduce PROGRAMMABLE_RESET_ADDRESS build option by Sandrine Bailleux · Tue Jun 02 17:19:43 2015 +0100
  31. acde8b0 Rationalize reset handling code by Sandrine Bailleux · Tue May 19 11:54:45 2015 +0100
  32. 22fa7e4 PSCI: Set ON_PENDING state early during CPU_ON by Soby Mathew · Mon May 11 23:15:06 2015 +0100
  33. ebfeae9 Pass arguments/results between EL3/S-EL1 via CPU registers (x0-x7) by Varun Wadekar · Thu Apr 02 14:57:47 2015 +0530
  34. a877c25 Add support to indicate size and end of assembly functions by Kévin Petit · Tue Mar 24 14:03:57 2015 +0000
  35. 2eb68ca Merge pull request #280 from vwadekar/tlkd-fixed-v3 by danh-arm · Wed Apr 01 11:36:08 2015 +0100
  36. b539b6c Open/Close TA sessions, send commands/events to TAs by Varun Wadekar · Fri Mar 13 15:18:20 2015 +0530
  37. 968c029 Preempt/Resume standard function ID calls by Varun Wadekar · Fri Mar 13 15:10:54 2015 +0530
  38. 97625e3 Translate secure/non-secure virtual addresses by Varun Wadekar · Fri Mar 13 14:59:03 2015 +0530
  39. a97535f Register NS shared memory for SP's activity logs and TA sessions by Varun Wadekar · Fri Mar 13 14:19:11 2015 +0530
  40. 3d4e6a5 Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd) by Varun Wadekar · Fri Mar 13 14:01:03 2015 +0530
  41. 9b38fc8 Initialise cpu ops after enabling data cache by Vikram Kanigiri · Thu Jan 29 18:27:38 2015 +0000
  42. a64a854 Fix violations to the coding style by Sandrine Bailleux · Thu Mar 05 10:54:34 2015 +0000
  43. 2b7de2b Export maximum affinity using PLATFORM_MAX_AFFLVL macro by Soby Mathew · Thu Feb 12 14:45:02 2015 +0000
  44. 36433d1 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · Thu Nov 20 18:09:41 2014 +0000
  45. 47903c0 Demonstrate model for routing IRQs to EL3 by Soby Mathew · Tue Jan 13 15:48:26 2015 +0000
  46. 61e615b Verify capabilities before handling PSCI calls by Soby Mathew · Thu Jan 15 11:49:49 2015 +0000
  47. 6cdddaf Implement PSCI_FEATURES API by Soby Mathew · Wed Jan 07 11:10:22 2015 +0000
  48. 110fe36 Rework the PSCI migrate APIs by Soby Mathew · Thu Oct 23 10:35:34 2014 +0100
  49. 26fb90e Return success if an interrupt is seen during PSCI CPU_SUSPEND by Soby Mathew · Tue Jan 06 21:36:55 2015 +0000
  50. 74e52a7 Validate power_state and entrypoint when executing PSCI calls by Soby Mathew · Thu Oct 02 16:56:51 2014 +0100
  51. f512157 Save 'power_state' early in PSCI CPU_SUSPEND call by Soby Mathew · Tue Sep 30 11:19:51 2014 +0100
  52. 8595b87 Rework internal API to save non-secure entry point info by Soby Mathew · Tue Jan 06 15:36:38 2015 +0000
  53. 5f2c1b3 PSCI: Check early for invalid CPU state during CPU ON by Soby Mathew · Mon Jan 12 13:01:31 2015 +0000
  54. ffb4ab1 Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops by Soby Mathew · Fri Sep 26 15:08:52 2014 +0100
  55. 2ae2043 Remove coherent memory from the BL memory maps by Soby Mathew · Thu Jan 08 18:02:44 2015 +0000
  56. 523d633 Move bakery algorithm implementation out of coherent memory by Soby Mathew · Thu Jan 08 18:02:19 2015 +0000
  57. 7d861ea Invalidate the dcache after initializing cpu-ops by Soby Mathew · Tue Nov 18 10:14:14 2014 +0000
  58. 2b69750 Fix CPU_SUSPEND when invoked with affinity level higher than get_max_afflvl() by Soby Mathew · Thu Oct 02 17:24:19 2014 +0100
  59. e2b2d8f Fix the array size of mpidr_aff_map_nodes_t. by Soby Mathew · Thu Dec 04 14:14:12 2014 +0000
  60. c288886 Add opteed based on tspd by Jens Wiklander · Mon Aug 04 15:39:58 2014 +0200
  61. 8e2f287 Add CPU specific power management operations by Soby Mathew · Thu Aug 14 12:49:05 2014 +0100
  62. 56bcdc2 Miscellaneous PSCI code cleanups by Achin Gupta · Mon Jul 28 00:15:23 2014 +0100
  63. f6b9e99 Add APIs to preserve highest affinity level in OFF state by Achin Gupta · Thu Jul 31 11:19:11 2014 +0100
  64. cab78e4 Rework state management in the PSCI implementation by Achin Gupta · Mon Jul 28 00:09:01 2014 +0100
  65. f3ccbab Add PSCI service specific per-CPU data by Achin Gupta · Fri Jul 25 14:52:47 2014 +0100
  66. 4dc4a47 Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs by Juan Castillo · Tue Aug 12 11:17:06 2014 +0100
  67. 9e46188 Merge pull request #189 from achingupta/ag/tf-issues#153 by Dan Handley · Tue Aug 19 11:04:21 2014 +0100
  68. 4fd2f5c Clarify platform porting interface to TSP by Dan Handley · Mon Aug 04 11:41:20 2014 +0100
  69. ed1744e Unmask SError interrupt and clear SCR_EL3.EA bit by Achin Gupta · Mon Aug 04 23:13:10 2014 +0100
  70. 6dc22e3 Merge pull request #178 from soby-mathew/sm/optmize_el3_context by danh-arm · Mon Aug 04 10:31:54 2014 +0100
  71. 4e81341 Support asynchronous method for BL3-2 initialization by Vikram Kanigiri · Tue Jul 15 16:49:22 2014 +0100
  72. 9d70f0f Rework the TSPD setup code by Vikram Kanigiri · Tue Jul 15 16:46:43 2014 +0100
  73. 2ed46e9 Optimize EL3 register state stored in cpu_context structure by Soby Mathew · Fri Jul 04 16:02:26 2014 +0100
  74. 5cd545d Merge pull request #177 from jcastillo-arm/jc/tf-issues/096 by danh-arm · Mon Jul 28 14:33:44 2014 +0100
  75. f558cac Rework incorrect use of assert() and panic() in codebase by Juan Castillo · Thu Jun 05 09:45:36 2014 +0100
  76. 9f09835 Simplify management of SCTLR_EL3 and SCTLR_EL1 by Achin Gupta · Fri Jul 18 18:38:28 2014 +0100
  77. 9c60d80 Remove the concept of coherent stacks by Achin Gupta · Thu Jun 26 11:12:37 2014 +0100
  78. e1aa516 Remove coherent stack usage from the warm boot path by Achin Gupta · Thu Jun 26 09:58:52 2014 +0100
  79. e998254 Make enablement of the MMU more flexible by Achin Gupta · Thu Jun 26 08:59:07 2014 +0100
  80. 2bc0785 Remove current CPU mpidr from PSCI common code by Andrew Thoelke · Mon Jun 09 12:44:21 2014 +0100
  81. 3c74a44 Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2 by danh-arm · Tue Jun 24 16:48:31 2014 +0100
  82. 42970b0 Merge pull request #147 from athoelke/at/remove-bakery-mpidr by danh-arm · Tue Jun 24 16:44:12 2014 +0100
  83. 2d55240 Remove all checkpatch errors from codebase by Juan Castillo · Fri Jun 13 17:05:10 2014 +0100
  84. 958cc02 Remove calling CPU mpidr from bakery lock API by Andrew Thoelke · Mon Jun 09 12:54:15 2014 +0100
  85. fb06094 Merge pull request #145 from athoelke/at/psci-memory-optimization-v2 by danh-arm · Mon Jun 23 18:04:29 2014 +0100
  86. dc589aa Merge pull request #144 from athoelke/at/init-context-v2 by danh-arm · Mon Jun 23 18:02:36 2014 +0100
  87. 56f4470 Correctly dimension the PSCI aff_map_node array by Andrew Thoelke · Fri Jun 20 00:36:14 2014 +0100
  88. e9a0d11 Eliminate psci_suspend_context array by Andrew Thoelke · Fri Jun 20 00:38:03 2014 +0100
  89. 4e12607 Initialise CPU contexts from entry_point_info by Andrew Thoelke · Wed Jun 04 21:10:52 2014 +0100
  90. 4af473c Merge pull request #140 from athoelke/at/psci_smc_handler by danh-arm · Mon Jun 23 14:40:20 2014 +0100
  91. 4d2d553 Remove early_exceptions from BL3-1 by Andrew Thoelke · Mon Jun 02 12:38:12 2014 +0100
  92. 8c28fe0 Per-cpu data cache restructuring by Andrew Thoelke · Mon Jun 02 11:40:35 2014 +0100
  93. a2f6553 Provide cm_get/set_context() for current CPU by Andrew Thoelke · Wed May 14 17:09:32 2014 +0100
  94. 89a3c84 PSCI SMC handler improvements by Andrew Thoelke · Tue Jun 10 16:37:37 2014 +0100
  95. 93c89ec Fix compilation issue for IMF_READ_INTERRUPT_ID build flag by Soby Mathew · Wed May 28 17:14:36 2014 +0100
  96. 459df4c Merge pull request #110 from soby-mathew:sm/support_normal_irq_in_tsp-v4 into for-v0.4 by Dan Handley · Tue May 27 18:46:22 2014 +0100
  97. 701fea7 Further renames of platform porting functions by Dan Handley · Tue May 27 16:17:21 2014 +0100
  98. 3d57851 Fixup Standard SMC Resume Handling by Soby Mathew · Tue May 27 10:20:01 2014 +0100
  99. b226a4d Add enable mmu platform porting interfaces by Dan Handley · Fri May 16 14:08:45 2014 +0100
  100. ed6ff95 Split platform.h into separate headers by Dan Handley · Wed May 14 17:44:19 2014 +0100