- 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · 1 year, 6 months ago
- a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 11 months ago
- f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago
- 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years, 6 months ago
- a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 7 months ago
- 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years, 6 months ago
- a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 8 months ago
- 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 8 months ago