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git01.mediatek.com / filogic / atf / 344ca9d20f69c6f03b6829fecb2092fcc753e94c / plat / intel / soc / common
  1. 2f2b61c fix(intel): remove unused printout by Sieu Mun Tang · Fri May 13 16:42:42 2022 +0800
  2. c366760 fix(intel): fix configuration status based on start request by Sieu Mun Tang · Fri May 13 14:55:05 2022 +0800
  3. 4f5554c style(intel): align the sequence in header file by Sieu Mun Tang · Fri May 13 14:36:32 2022 +0800
  4. 7420c53 fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD by Sieu Mun Tang · Tue May 10 23:17:04 2022 +0800
  5. 527df9f fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying by Sieu Mun Tang · Thu Apr 28 16:28:48 2022 +0800
  6. e77d37d fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying by Sieu Mun Tang · Thu Apr 28 16:23:20 2022 +0800
  7. 9bea815 fix(intel): extending to support large file size for AES encryption and decryption by Sieu Mun Tang · Thu Apr 28 16:15:54 2022 +0800
  8. 5d187c0 feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands by Sieu Mun Tang · Tue May 10 23:26:57 2022 +0800
  9. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · Wed May 11 10:45:19 2022 +0800
  10. d2df204 fix(intel): update certificate mask for FPGA Attestation by Boon Khai Ng · Mon Aug 30 15:05:49 2021 +0800
  11. 758a2ad feat(intel): update to support maximum response data size by Sieu Mun Tang · Wed May 11 10:23:13 2022 +0800
  12. 59357e8 feat(intel): support ECDSA HASH Verification by Sieu Mun Tang · Tue May 10 17:53:32 2022 +0800
  13. 8aa05ad feat(intel): support ECDSA HASH Signing by Sieu Mun Tang · Tue May 10 17:50:30 2022 +0800
  14. 0675c22 feat(intel): support ECDH request by Sieu Mun Tang · Tue May 10 17:48:11 2022 +0800
  15. dcaab77 feat(intel): support ECDSA SHA-2 Data Signature Verification by Sieu Mun Tang · Wed May 11 10:16:40 2022 +0800
  16. 153ecfb feat(intel): support ECDSA SHA-2 Data Signing by Sieu Mun Tang · Tue May 10 17:39:26 2022 +0800
  17. e2f3ede feat(intel): support ECDSA Get Public Key by Sieu Mun Tang · Tue May 10 17:36:32 2022 +0800
  18. 22322fb feat(intel): support session based SDOS encrypt and decrypt by Sieu Mun Tang · Mon May 09 16:05:58 2022 +0800
  19. b0c1d11 feat(intel): support AES Crypt Service by Sieu Mun Tang · Tue May 10 17:30:00 2022 +0800
  20. 583149a feat(intel): support HMAC SHA-2 MAC verify request by Sieu Mun Tang · Tue May 10 17:27:12 2022 +0800
  21. d907cc3 feat(intel): support SHA-2 hash digest generation on a blob by Sieu Mun Tang · Tue May 10 17:24:05 2022 +0800
  22. e7a037f feat(intel): support extended random number generation by Sieu Mun Tang · Tue May 10 17:18:19 2022 +0800
  23. fb1f6e9 feat(intel): support crypto service key operation by Sieu Mun Tang · Mon May 09 14:16:14 2022 +0800
  24. 16754e1 feat(intel): support crypto service session by Sieu Mun Tang · Mon May 09 12:08:42 2022 +0800
  25. 28af165 feat(intel): extend attestation service to Agilex family by Sieu Mun Tang · Mon May 09 10:48:53 2022 +0800
  26. cac786d fix(intel): flush dcache before sending certificate to mailbox by Boon Khai Ng · Wed May 26 01:50:34 2021 +0800
  27. 96bbdca fix(intel): introduce a generic response error code by Sieu Mun Tang · Tue Apr 12 15:00:13 2022 +0800
  28. fd8a8ad fix(intel): allow non-secure access to FPGA Crypto Services (FCS) by Sieu Mun Tang · Sat May 07 00:50:37 2022 +0800
  29. a068fdf feat(intel): single certificate feature enablement by Sieu Mun Tang · Wed May 11 10:01:54 2022 +0800
  30. 2a820b9 feat(intel): initial commit for attestation service by Sieu Mun Tang · Wed May 11 09:59:55 2022 +0800
  31. 128d2a7 fix(intel): update encryption and decryption command logic by Sieu Mun Tang · Wed May 11 09:49:25 2022 +0800
  32. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  33. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  34. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  35. db79fa5 fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS) by Sieu Mun Tang · Sun Mar 20 00:49:57 2022 +0800
  36. e768dfa feat(intel): add SMC support for HWMON voltage and temp sensor by Kris Chaplin · Fri Jun 25 11:31:52 2021 +0100
  37. 2b8e005 feat(intel): add SMC support for Get USERCODE by Sieu Mun Tang · Wed Apr 27 18:57:29 2022 +0800
  38. bfda95a fix(intel): extend SDM command to return the SDM firmware version by Sieu Mun Tang · Wed Apr 27 18:54:10 2022 +0800
  39. d9006fc feat(intel): add SMC for enquiring firmware version by Abdul Halim, Muhammad Hadi Asyrafi · Fri Feb 05 11:50:58 2021 +0800
  40. 959143d fix(intel): configuration status based on start request by Abdul Halim, Muhammad Hadi Asyrafi · Tue Dec 29 16:49:23 2020 +0800
  41. 5406498 fix(intel): bit-wise configuration flag handling by Sieu Mun Tang · Thu Apr 28 22:40:58 2022 +0800
  42. 37c7076 fix(intel): get config status OK status by Abdul Halim, Muhammad Hadi Asyrafi · Fri Nov 20 11:41:59 2020 +0800
  43. fbc3913 fix(intel): use macro as return value by Abdul Halim, Muhammad Hadi Asyrafi · Fri Nov 20 11:06:00 2020 +0800
  44. 351e884 fix(intel): fix fpga config write return mechanism by Abdul Halim, Muhammad Hadi Asyrafi · Thu Nov 05 18:00:03 2020 +0800
  45. e6d5de9 feat(intel): add SiP service for DCMF status by Sieu Mun Tang · Thu Apr 28 22:21:01 2022 +0800
  46. 681631b feat(intel): add RSU 'Max Retry' SiP SMC services by Chee Hong Ang · Wed Jul 01 14:22:25 2020 +0800
  47. b30ce3f feat(intel): enable SMC SoC FPGA bridges enable/disable by Abdul Halim, Muhammad Hadi Asyrafi · Thu Jun 18 16:21:29 2020 +0800
  48. 2cfd8ec feat(intel): add SMC/PSCI services for DCMF version support by Chee Hong Ang · Wed May 13 11:44:04 2020 +0800
  49. 869d4f5 feat(intel): allow to access all register addresses if DEBUG=1 by Siew Chin Lim · Tue May 11 21:12:22 2021 +0800
  50. b251c33 fix(intel): modify how configuration type is handled by Abdul Halim, Muhammad Hadi Asyrafi · Fri May 29 12:13:17 2020 +0800
  51. f9cb657 feat(intel): support SiP SVC version by Sieu Mun Tang · Wed Apr 27 18:24:06 2022 +0800
  52. 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:40:46 2020 +0800
  53. 1205ef0 feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · Thu Aug 06 10:21:54 2020 +0800
  54. 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · Wed Aug 05 22:12:23 2020 +0800
  55. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · Fri Aug 06 01:16:46 2021 +0800
  56. a34b881 feat(intel): add SMC support for ROM Patch SHA384 mailbox by Sieu Mun Tang · Thu Mar 17 03:11:55 2022 +0800
  57. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · Fri May 21 22:56:37 2021 +0800
  58. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  59. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · Mon Mar 07 12:13:04 2022 +0800
  60. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · Mon Jun 29 12:15:27 2020 +0800
  61. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · Mon Mar 07 12:04:59 2022 +0800
  62. 9f22cbf build(intel): initial commit for crypto driver by Sieu Mun Tang · Wed Mar 02 11:04:09 2022 +0800
  63. f57b5cc Merge changes I75b3e3bf,I4cf9f1d9,I50d2ae74,Idbe62410,I84bbd06e, ... into integration by Madhukar Pappireddy · Mon Feb 28 17:18:39 2022 +0100
  64. 2468266 fix(intel): null pointer handling for resp_len by Sieu Mun Tang · Sat Feb 19 21:49:48 2022 +0800
  65. 33b89d5 fix(intel): define macros to handle buffer entries by Abdul Halim, Muhammad Hadi Asyrafi · Fri Jun 05 15:12:29 2020 +0800
  66. f02f0cb fix(intel): change SMC return arguments for INTEL_SIP_SMC_MBOX_SEND_CMD by Sieu Mun Tang · Sat Feb 19 20:36:41 2022 +0800
  67. bf90984 fix(intel): always set doorbell to SDM after sending command by Siew Chin Lim · Fri Jul 30 00:40:48 2021 +0800
  68. a076315 fix(intel): fix bit masking issue in intel_secure_reg_update by Siew Chin Lim · Sat Jul 10 00:55:35 2021 +0800
  69. 461f544 fix(intel): fix ddr address range checker by Abdul Halim, Muhammad Hadi Asyrafi · Fri Jul 03 13:22:09 2020 +0800
  70. ae4cd3a fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · Tue Oct 06 20:09:53 2020 +0800
  71. 118ab21 intel: common: Fix non-MISRA compliant code v2 by Abdul Halim, Muhammad Hadi Asyrafi · Thu Oct 15 15:27:18 2020 +0800
  72. 1b0e8cb intel: mailbox: Fix non-MISRA compliant code by Abdul Halim, Muhammad Hadi Asyrafi · Tue Sep 01 21:05:18 2020 +0800
  73. 5bc87bc intel: mailbox: Mailbox error recovery handling by Chee Hong Ang · Mon May 11 11:23:21 2020 +0800
  74. 7d66e14 intel: mailbox: Enable sending large mailbox command by Abdul Halim, Muhammad Hadi Asyrafi · Tue Jun 02 01:06:33 2020 +0800
  75. 14a1d43 intel: mailbox: Use retry count in mailbox poll by Abdul Halim, Muhammad Hadi Asyrafi · Tue Jun 02 01:05:24 2020 +0800
  76. 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · Mon May 11 00:55:01 2020 +0800
  77. 39d137b intel: mailbox: Read mailbox response even there is an error by Chee Hong Ang · Mon May 11 00:40:18 2020 +0800
  78. 94fae38 intel: mailbox: Driver now handles larger response by Abdul Halim, Muhammad Hadi Asyrafi · Wed Apr 29 22:26:40 2020 +0800
  79. 20a07f3 intel: common: Change how mailbox handles job id & buffer by Abdul Halim, Muhammad Hadi Asyrafi · Mon May 18 11:16:48 2020 +0800
  80. 046e1f1 intel: common: Improve readability of mailbox read response by Abdul Halim, Muhammad Hadi Asyrafi · Wed Feb 12 19:57:44 2020 +0800
  81. 99b5e16 intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB by Richard Gong · Mon Apr 13 09:40:43 2020 -0500
  82. 2b7d13e intel: common: Remove urgent from mailbox async by Abdul Halim, Muhammad Hadi Asyrafi · Mon May 18 10:32:15 2020 +0800
  83. b45f15e intel: common: Improve mailbox driver readability by Abdul Halim, Muhammad Hadi Asyrafi · Thu May 14 15:32:43 2020 +0800
  84. ec164b6 intel: common: Clean up mailbox and sip header by Abdul Halim, Muhammad Hadi Asyrafi · Thu May 14 14:53:29 2020 +0800
  85. 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · Fri Apr 24 21:51:00 2020 +0800
  86. 64d2b2f plat: intel: Additional instruction required to enable global timer by Tien Hock Loh · Mon May 11 01:12:03 2020 -0700
  87. 070ffbb plat: intel: Fix CCU initialization for Agilex by Tien Hock Loh · Mon May 11 01:11:55 2020 -0700
  88. c5baddf plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · Mon May 11 01:11:48 2020 -0700
  89. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · Mon May 11 01:11:39 2020 -0700
  90. 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · Fri Feb 28 10:51:49 2020 +0000
  91. 6bedfe2 Merge "intel: Fix argument type for mailbox driver" into integration by Sandrine Bailleux · Fri Feb 28 10:23:10 2020 +0000
  92. 25f623e intel: Update RSU driver return code by Abdul Halim, Muhammad Hadi Asyrafi · Thu Feb 27 10:23:48 2020 +0800
  93. d84bfef intel: Fix argument type for mailbox driver by Abdul Halim, Muhammad Hadi Asyrafi · Tue Feb 25 16:28:10 2020 +0800
  94. 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · Wed Oct 02 13:49:25 2019 +0800
  95. c4c4dec Merge "intel: Fix Coverity Scan Defects" into integration by Sandrine Bailleux · Thu Feb 20 09:53:26 2020 +0000
  96. e59b999 intel: Fix Coverity Scan Defects by Abdul Halim, Muhammad Hadi Asyrafi · Tue Feb 11 20:17:05 2020 +0800
  97. 7f95059 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · Wed Feb 12 15:54:02 2020 +0000
  98. c39a0e0 intel: Include address range check for SiP Mailbox by Abdul Halim, Muhammad Hadi Asyrafi · Thu Feb 06 19:18:41 2020 +0800
  99. a33e810 intel: Introduce SMC support for mailbox command by Hadi Asyrafi · Tue Dec 17 19:30:41 2019 +0800
  100. 593c4c5 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · Tue Dec 17 19:22:17 2019 +0800