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git01.mediatek.com / filogic / atf / 2664db429c8fd394528cb4aeade3dde36a6ea394 / plat / intel / soc / n5x
  1. 4c249f1 feat(intel): platform enablement for Agilex5 SoC FPGA by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  2. 28c1c78 feat(intel): restructure sys mgr for S10/N5X by Jit Loon Lim · Wed May 17 12:26:11 2023 +0800
  3. 2be03c0 fix(tree): correct some typos by Elyes Haouas · Mon Feb 13 09:14:48 2023 +0100
  4. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · Thu Dec 22 21:52:36 2022 +0800
  5. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · Thu Jun 23 18:05:02 2022 +0800
  6. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  7. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · Fri Jul 01 09:08:57 2022 +0800
  8. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · Wed May 11 10:45:19 2022 +0800
  9. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · Tue May 10 20:17:51 2022 +0200
  10. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · Wed Apr 06 10:19:16 2022 +0800
  11. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · Thu May 05 17:07:21 2022 +0800
  12. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · Fri Aug 06 01:16:46 2021 +0800
  13. 1e5550b build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · Fri May 21 22:56:37 2021 +0800
  14. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · Mon Feb 28 15:24:59 2022 +0800
  15. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · Mon Mar 07 12:13:04 2022 +0800
  16. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · Mon Jun 29 12:15:27 2020 +0800
  17. 8881ad0 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · Mon Mar 07 12:04:59 2022 +0800