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git01.mediatek.com / filogic / atf / 1f9eab759d942b1f091c3a2f6edff8afca89e985 / plat / intel / soc / agilex / bl2_plat_setup.c
  1. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 4 years, 6 months ago
  2. 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · 4 years, 8 months ago
  3. 98b5a11 16550: Use generic console_t data structure by Andre Przywara · 4 years, 9 months ago
  4. 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · 5 years ago
  5. 786db4d intel: Change boot source selection by Hadi Asyrafi · 4 years, 10 months ago
  6. 6aeb55d intel: Add function to check fpga readiness by Hadi Asyrafi · 4 years, 10 months ago
  7. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · 4 years, 11 months ago
  8. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · 4 years, 11 months ago
  9. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · 5 years ago
  10. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · 5 years ago
  11. 5ae876f intel: Refactor common platform code [5/5] by Hadi Asyrafi · 5 years ago
  12. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · 5 years ago
  13. f0fa807 intel: Refactor common platform code [2/5] by Hadi Asyrafi · 5 years ago
  14. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 5 years ago
  15. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  16. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago