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git01.mediatek.com / filogic / atf / 153db957d25de4f27968d9769024f685f5aae6df / include / arch / aarch64 / el3_common_macros.S
  1. 71af7f1 feat(spmd): initialize SCR_EL3.EEL2 bit at RESET by Manish Pandey · Mon Jan 29 21:17:33 2024 +0000
  2. 514a301 fix(ras): restrict ENABLE_FEAT_RAS to have only two states by Manish Pandey · Tue Oct 10 13:53:25 2023 +0100
  3. 6b5721f feat(ras): use FEAT_IESB for error synchronization by Manish Pandey · Mon Jun 26 17:46:14 2023 +0100
  4. 4fc00d2 refactor(cm): move EL3 registers to global context by Elizabeth Ho · Tue Jul 18 14:10:25 2023 +0100
  5. 2e9e6f0 refactor(cm): remove world differentiation for EL2 context restore by Boyan Karatotev · Mon May 22 15:53:58 2023 +0100
  6. 8ae58f0 refactor(cm): clean up SCR_EL3 and CPTR_EL3 initialization by Boyan Karatotev · Thu Apr 20 11:00:50 2023 +0100
  7. 919d3c8 refactor(cm): set MDCR_EL3/CPTR_EL3 bits in respective feat_init_el3() only by Boyan Karatotev · Mon Feb 13 16:32:47 2023 +0000
  8. 677ed8a refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init by Boyan Karatotev · Thu Feb 16 09:45:29 2023 +0000
  9. 05504ba feat(pmu): introduce pmuv3 lib/extensions folder by Boyan Karatotev · Wed Feb 15 13:21:50 2023 +0000
  10. 1f55c41 refactor(cpufeat): enable FEAT_DIT for FEAT_STATE_CHECKED by Andre Przywara · Thu Jan 26 16:47:52 2023 +0000
  11. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · Tue Nov 22 14:41:00 2022 -0600
  12. 259b6d0 Merge changes from topic "panic_cleanup" into integration by Bipin Ravi · Thu Feb 23 23:38:26 2023 +0100
  13. a796b1b refactor(aarch64): rename do_panic and el3_panic by Govindraj Raja · Mon Jan 16 17:35:07 2023 +0000
  14. 66a056e refactor(el3_runtime): introduce save_x30 macro by Manish Pandey · Wed Jan 11 21:41:07 2023 +0000
  15. 0824b45 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · Thu Feb 24 10:47:33 2022 +0800
  16. 928747f fix(el3-runtime): set unset pstate bits to default by Daniel Boulby · Tue May 25 18:09:34 2021 +0100
  17. 9baade3 feat(sme): enable SME functionality by johpow01 · Thu Jul 08 14:14:00 2021 -0500
  18. b0d69e8 fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · Fri Oct 15 17:25:52 2021 -0500
  19. 688fbf7 feat(rme): run BL2 in root world when FEAT_RME is enabled by Zelalem Aweke · Fri Jul 09 11:37:10 2021 -0500
  20. 8ce3394 feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · Sun Jul 18 02:26:27 2021 +0100
  21. f7ee064 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · Wed Jul 07 16:27:10 2021 +0100
  22. e1cccb4 feat(trbe): initialize trap settings of trace buffer control registers access by Manish V Badarkhe · Wed Jun 23 20:02:39 2021 +0100
  23. c450277 feat(sve): enable SVE for the secure world by Max Shvetsov · Mon Mar 22 11:59:37 2021 +0000
  24. 307f34b fix(security): Set MDCR_EL3.MCCD bit by Alexei Fedorov · Fri May 14 11:21:56 2021 +0100
  25. f3a4c54 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · Mon Nov 23 18:38:15 2020 +0000
  26. ed20207 Increase type widths to satisfy width requirements by Jimmy Brisson · Tue Aug 04 16:18:52 2020 -0500
  27. e07e808 runtime_exceptions: Update AT speculative workaround by Manish V Badarkhe · Thu Jul 23 12:43:25 2020 +0100
  28. 5dc9e9c Fix compilation error when ENABLE_PIE=1 by Varun Wadekar · Sat May 16 20:59:30 2020 -0700
  29. 31a14e1 bl31: Split into two separate memory regions by Samuel Holland · Wed Oct 17 21:40:18 2018 -0500
  30. c825768 PIE: make call to GDT relocation fixup generalized by Manish Pandey · Tue Nov 26 11:34:17 2019 +0000
  31. add24a4 Explicitly disable the SPME bit in MDCR_EL3 by Petre-Ionut Tudor · Thu Oct 03 17:09:08 2019 +0100
  32. d2f21b8 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · Mon May 27 09:32:00 2019 +0200
  33. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · Tue Aug 20 15:33:27 2019 +0800
  34. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  35. 594811b Add ARMv8.3-PAuth registers to CPU context by Antonio Nino Diaz · Thu Jan 31 11:58:00 2019 +0000
  36. 3fbd3f5 Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · Mon Feb 18 16:55:43 2019 +0000
  37. 8d1ade6 Reorganize architecture-dependent header files by Antonio Nino Diaz · Mon Dec 17 17:20:57 2018 +0000[Renamed from include/common/aarch64/el3_common_macros.S]
  38. 0f3a004 Merge pull request #1731 from miyatsu/doc-fix-20181225 by Antonio Niño Díaz · Fri Jan 04 09:14:22 2019 +0000