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git01.mediatek.com / filogic / atf / 02c35681e67b4efe809139854e0324e133d39e98 / plat / intel / soc / agilex
  1. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · Tue Aug 20 15:33:27 2019 +0800
  2. 91071fc intel: agilex: Fix psci power domain off by Hadi Asyrafi · Thu Sep 12 15:14:01 2019 +0800
  3. cc077d9 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · Wed Aug 28 13:05:51 2019 +0000
  4. 5d7c656 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · Fri Aug 16 17:07:42 2019 +0800
  5. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · Fri Aug 16 11:08:14 2019 +0800
  6. ad90712 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · Thu Aug 15 15:30:51 2019 +0000
  7. 83fe38e intel: agilex: Fix memory controller driver by Hadi Asyrafi · Thu Aug 08 18:52:31 2019 +0800
  8. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · Wed Aug 14 13:49:00 2019 +0800
  9. 462c6c4 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · Wed Aug 07 14:20:01 2019 +0000
  10. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 14:48:39 2019 +0800
  11. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · Thu Aug 01 15:21:20 2019 +0800
  12. e944d22 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · Tue Jul 30 10:56:38 2019 +0800
  13. a724e43 intel: agilex: Fix build error by Ambroise Vincent · Tue Jul 23 11:10:27 2019 +0100
  14. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · Thu Jun 27 11:34:03 2019 +0800