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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
Yann Gautiere7534702019-02-14 11:14:18 +01003 * Copyright (c) 2018-2019, Linaro Limited
Yann Gautieree8f5422019-02-14 11:13:25 +01004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef STM32MP_COMMON_H
9#define STM32MP_COMMON_H
10
Yann Gautiera2e2a302019-02-14 11:13:39 +010011#include <stdbool.h>
12
Yann Gautiere7534702019-02-14 11:14:18 +010013#include <arch_helpers.h>
14
Yann Gautieree8f5422019-02-14 11:13:25 +010015/* Functions to save and get boot context address given by ROM code */
Yann Gautiera2e2a302019-02-14 11:13:39 +010016void stm32mp_save_boot_ctx_address(uintptr_t address);
17uintptr_t stm32mp_get_boot_ctx_address(void);
Yann Gautieree8f5422019-02-14 11:13:25 +010018
Yann Gautier3d78a2e2019-02-14 11:01:20 +010019/* Return the base address of the DDR controller */
20uintptr_t stm32mp_ddrctrl_base(void);
21
22/* Return the base address of the DDR PHY */
23uintptr_t stm32mp_ddrphyc_base(void);
24
25/* Return the base address of the PWR peripheral */
26uintptr_t stm32mp_pwr_base(void);
27
28/* Return the base address of the RCC peripheral */
29uintptr_t stm32mp_rcc_base(void);
30
Yann Gautieree8f5422019-02-14 11:13:25 +010031/*
32 * Platform util functions for the GPIO driver
33 * @bank: Target GPIO bank ID as per DT bindings
34 *
35 * Platform shall implement these functions to provide to stm32_gpio
36 * driver the resource reference for a target GPIO bank. That are
37 * memory mapped interface base address, interface offset (see below)
38 * and clock identifier.
39 *
40 * stm32_get_gpio_bank_offset() returns a bank offset that is used to
41 * check DT configuration matches platform implementation of the banks
42 * description.
43 */
44uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
45unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
46uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
47
Yann Gautiera2e2a302019-02-14 11:13:39 +010048/*
49 * Util for clock gating and to get clock rate for stm32 and platform drivers
50 * @id: Target clock ID, ID used in clock DT bindings
51 */
52bool stm32mp_clk_is_enabled(unsigned long id);
Yann Gautiere4a3c352019-02-14 10:53:33 +010053void stm32mp_clk_enable(unsigned long id);
54void stm32mp_clk_disable(unsigned long id);
Yann Gautiera2e2a302019-02-14 11:13:39 +010055unsigned long stm32mp_clk_get_rate(unsigned long id);
56
Yann Gautieree8f5422019-02-14 11:13:25 +010057/* Initialise the IO layer and register platform IO devices */
Yann Gautiera2e2a302019-02-14 11:13:39 +010058void stm32mp_io_setup(void);
Yann Gautieree8f5422019-02-14 11:13:25 +010059
Yann Gautiere7534702019-02-14 11:14:18 +010060static inline uint64_t arm_cnt_us2cnt(uint32_t us)
61{
62 return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
63}
64
65static inline uint64_t timeout_init_us(uint32_t us)
66{
67 return read_cntpct_el0() + arm_cnt_us2cnt(us);
68}
69
70static inline bool timeout_elapsed(uint64_t expire)
71{
72 return read_cntpct_el0() > expire;
73}
74
Yann Gautieree8f5422019-02-14 11:13:25 +010075#endif /* STM32MP_COMMON_H */