blob: 42e6a1f7cca6251b3962ad06aa955a9e9332290e [file] [log] [blame]
Varun Wadekarb3741032017-09-25 13:27:45 -07001/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef IVC_H
8#define IVC_H
9
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000010#include <lib/utils_def.h>
Varun Wadekarb3741032017-09-25 13:27:45 -070011#include <stdint.h>
12#include <stddef.h>
Varun Wadekarb3741032017-09-25 13:27:45 -070013
14#define IVC_ALIGN U(64)
15#define IVC_CHHDR_TX_FIELDS U(16)
16#define IVC_CHHDR_RX_FIELDS U(16)
17
18struct ivc;
19struct ivc_channel_header;
20
21/* callback handler for notify on receiving a response */
22typedef void (* ivc_notify_function)(const struct ivc *);
23
24struct ivc {
25 struct ivc_channel_header *rx_channel;
26 struct ivc_channel_header *tx_channel;
27 uint32_t w_pos;
28 uint32_t r_pos;
29 ivc_notify_function notify;
30 uint32_t nframes;
31 uint32_t frame_size;
32};
33
34int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
35 uint32_t nframes, uint32_t frame_size,
36 ivc_notify_function notify);
37size_t tegra_ivc_total_queue_size(size_t queue_size);
38size_t tegra_ivc_align(size_t size);
39int32_t tegra_ivc_channel_notified(struct ivc *ivc);
40void tegra_ivc_channel_reset(const struct ivc *ivc);
41int32_t tegra_ivc_write_advance(struct ivc *ivc);
42void *tegra_ivc_write_get_next_frame(const struct ivc *ivc);
43int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size);
44int32_t tegra_ivc_read_advance(struct ivc *ivc);
45void *tegra_ivc_read_get_next_frame(const struct ivc *ivc);
46int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read);
47bool tegra_ivc_tx_empty(const struct ivc *ivc);
48bool tegra_ivc_can_write(const struct ivc *ivc);
49bool tegra_ivc_can_read(const struct ivc *ivc);
50
51#endif /* IVC_H */