Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022-2023, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_x4.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
| 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
| 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 29 | workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 30 | #if IMAGE_BL31 |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 31 | /* |
| 32 | * The Cortex X4 generic vectors are overridden to apply errata |
| 33 | * mitigation on exception entry from lower ELs. |
| 34 | */ |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 35 | override_vector_table wa_cve_vbar_cortex_x4 |
| 36 | #endif /* IMAGE_BL31 */ |
| 37 | workaround_reset_end cortex_x4, CVE(2022, 23960) |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 38 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 39 | check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 40 | |
| 41 | cpu_reset_func_start cortex_x4 |
| 42 | /* Disable speculative loads */ |
| 43 | msr SSBS, xzr |
| 44 | cpu_reset_func_end cortex_x4 |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 45 | |
| 46 | /* ---------------------------------------------------- |
| 47 | * HW will do the cache maintenance while powering down |
| 48 | * ---------------------------------------------------- |
| 49 | */ |
| 50 | func cortex_x4_core_pwr_dwn |
| 51 | /* --------------------------------------------------- |
| 52 | * Enable CPU power down bit in power control register |
| 53 | * --------------------------------------------------- |
| 54 | */ |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 55 | sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 56 | isb |
| 57 | ret |
| 58 | endfunc cortex_x4_core_pwr_dwn |
| 59 | |
Govindraj Raja | f362510 | 2023-04-24 15:21:19 -0500 | [diff] [blame] | 60 | errata_report_shim cortex_x4 |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 61 | |
| 62 | /* --------------------------------------------- |
| 63 | * This function provides Cortex X4-specific |
| 64 | * register information for crash reporting. |
| 65 | * It needs to return with x6 pointing to |
| 66 | * a list of register names in ascii and |
| 67 | * x8 - x15 having values of registers to be |
| 68 | * reported. |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | .section .rodata.cortex_x4_regs, "aS" |
| 72 | cortex_x4_regs: /* The ascii list of register names to be reported */ |
| 73 | .asciz "cpuectlr_el1", "" |
| 74 | |
| 75 | func cortex_x4_cpu_reg_dump |
| 76 | adr x6, cortex_x4_regs |
| 77 | mrs x8, CORTEX_X4_CPUECTLR_EL1 |
| 78 | ret |
| 79 | endfunc cortex_x4_cpu_reg_dump |
| 80 | |
| 81 | declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ |
| 82 | cortex_x4_reset_func, \ |
| 83 | cortex_x4_core_pwr_dwn |