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Xing Zhengb4bcc1d2017-02-24 16:26:11 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Xing Zhengb4bcc1d2017-02-24 16:26:11 +08005 */
6
7#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
8#define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
9
10#define SIZE_K(n) ((n) * 1024)
11#define SIZE_M(n) ((n) * 1024 * 1024)
Lin Huang88dd1232017-05-16 16:40:46 +080012#define SRAM_TEXT_LIMIT (4 * 1024)
13#define SRAM_DATA_LIMIT (4 * 1024)
14#define SRAM_BIN_LIMIT (4 * 1024)
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080015
16/*
17 * The parts of the shared defined registers address with AP and M0,
18 * let's note and mark the previous defines like this:
19 */
20#define GIC500_BASE (MMIO_BASE + 0x06E00000)
21#define UART0_BASE (MMIO_BASE + 0x07180000)
22#define UART1_BASE (MMIO_BASE + 0x07190000)
23#define UART2_BASE (MMIO_BASE + 0x071A0000)
24#define UART3_BASE (MMIO_BASE + 0x071B0000)
25
26#define PMU_BASE (MMIO_BASE + 0x07310000)
27#define PMUGRF_BASE (MMIO_BASE + 0x07320000)
28#define SGRF_BASE (MMIO_BASE + 0x07330000)
29#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000)
30#define PWM_BASE (MMIO_BASE + 0x07420000)
31
32#define CIC_BASE (MMIO_BASE + 0x07620000)
33#define PD_BUS0_BASE (MMIO_BASE + 0x07650000)
34#define DCF_BASE (MMIO_BASE + 0x076A0000)
35#define GPIO0_BASE (MMIO_BASE + 0x07720000)
36#define GPIO1_BASE (MMIO_BASE + 0x07730000)
37#define PMUCRU_BASE (MMIO_BASE + 0x07750000)
38#define CRU_BASE (MMIO_BASE + 0x07760000)
39#define GRF_BASE (MMIO_BASE + 0x07770000)
40#define GPIO2_BASE (MMIO_BASE + 0x07780000)
41#define GPIO3_BASE (MMIO_BASE + 0x07788000)
42#define GPIO4_BASE (MMIO_BASE + 0x07790000)
Lin Huang2c60b5f2017-05-18 18:04:25 +080043#define WDT1_BASE (MMIO_BASE + 0x07840000)
44#define WDT0_BASE (MMIO_BASE + 0x07848000)
45#define TIMER_BASE (MMIO_BASE + 0x07850000)
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080046#define STIME_BASE (MMIO_BASE + 0x07860000)
47#define SRAM_BASE (MMIO_BASE + 0x078C0000)
48#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
49#define DDRC0_BASE (MMIO_BASE + 0x07A80000)
50#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000)
51#define DDRC1_BASE (MMIO_BASE + 0x07A88000)
52#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000)
53#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000)
54#define CCI500_BASE (MMIO_BASE + 0x07B00000)
55#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000)
56
57/* Registers size */
58#define GIC500_SIZE SIZE_M(2)
59#define UART0_SIZE SIZE_K(64)
60#define UART1_SIZE SIZE_K(64)
61#define UART2_SIZE SIZE_K(64)
62#define UART3_SIZE SIZE_K(64)
63#define PMU_SIZE SIZE_K(64)
64#define PMUGRF_SIZE SIZE_K(64)
65#define SGRF_SIZE SIZE_K(64)
66#define PMUSRAM_SIZE SIZE_K(64)
67#define PMUSRAM_RSIZE SIZE_K(8)
68#define PWM_SIZE SIZE_K(64)
69#define CIC_SIZE SIZE_K(4)
70#define DCF_SIZE SIZE_K(4)
71#define GPIO0_SIZE SIZE_K(64)
72#define GPIO1_SIZE SIZE_K(64)
73#define PMUCRU_SIZE SIZE_K(64)
74#define CRU_SIZE SIZE_K(64)
75#define GRF_SIZE SIZE_K(64)
76#define GPIO2_SIZE SIZE_K(32)
77#define GPIO3_SIZE SIZE_K(32)
78#define GPIO4_SIZE SIZE_K(32)
79#define STIME_SIZE SIZE_K(64)
80#define SRAM_SIZE SIZE_K(192)
81#define SERVICE_NOC_0_SIZE SIZE_K(192)
82#define DDRC0_SIZE SIZE_K(32)
83#define SERVICE_NOC_1_SIZE SIZE_K(16)
84#define DDRC1_SIZE SIZE_K(32)
85#define SERVICE_NOC_2_SIZE SIZE_K(16)
86#define SERVICE_NOC_3_SIZE SIZE_K(448)
87#define CCI500_SIZE SIZE_M(1)
88#define PD_BUS0_SIZE SIZE_K(448)
89
90/* DDR Registers address */
91#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000)
92#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
93
94#define PI_OFFSET 0x800
95#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
96#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
97
98#define PHY_OFFSET 0x2000
99#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
100#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
101
102#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000)
103
104#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */