| Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <debug.h> |
| 9 | #include <platform_def.h> |
| 10 | #include <ddr_info.h> |
| 11 | #include <mmio.h> |
| 12 | |
| 13 | #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base) \ |
| 14 | (base + DRAM_CH0_MMAP_LOW_OFFSET + (iface) * 0x10000 + (cs) * 0x8) |
| 15 | #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base) \ |
| 16 | (DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4) |
| 17 | #define DRAM_CS_VALID_ENABLED_MASK 0x1 |
| 18 | #define DRAM_AREA_LENGTH_OFFS 16 |
| 19 | #define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) |
| 20 | #define DRAM_START_ADDRESS_L_OFFS 23 |
| 21 | #define DRAM_START_ADDRESS_L_MASK \ |
| 22 | (0x1ff << DRAM_START_ADDRESS_L_OFFS) |
| 23 | #define DRAM_START_ADDR_HTOL_OFFS 32 |
| 24 | |
| 25 | #define DRAM_MAX_CS_NUM 2 |
| 26 | |
| 27 | #define DRAM_CS_ENABLED(iface, cs, base) \ |
| 28 | (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \ |
| 29 | DRAM_CS_VALID_ENABLED_MASK) |
| 30 | #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \ |
| 31 | (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \ |
| 32 | DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS |
| 33 | |
| 34 | /* Mapping between DDR area length and real DDR size is specific and looks like |
| 35 | * bellow: |
| 36 | * 0 => 384 MB |
| 37 | * 1 => 768 MB |
| 38 | * 2 => 1536 MB |
| 39 | * 3 => 3 GB |
| 40 | * 4 => 6 GB |
| 41 | * |
| 42 | * 7 => 8 MB |
| 43 | * 8 => 16 MB |
| 44 | * 9 => 32 MB |
| 45 | * 10 => 64 MB |
| 46 | * 11 => 128 MB |
| 47 | * 12 => 256 MB |
| 48 | * 13 => 512 MB |
| 49 | * 14 => 1 GB |
| 50 | * 15 => 2 GB |
| 51 | * 16 => 4 GB |
| 52 | * 17 => 8 GB |
| 53 | * 18 => 16 GB |
| 54 | * 19 => 32 GB |
| 55 | * 20 => 64 GB |
| 56 | * 21 => 128 GB |
| 57 | * 22 => 256 GB |
| 58 | * 23 => 512 GB |
| 59 | * 24 => 1 TB |
| 60 | * 25 => 2 TB |
| 61 | * 26 => 4 TB |
| 62 | * |
| 63 | * to calculate real size we need to use two different formulas: |
| 64 | * -- GET_DRAM_REGION_SIZE_ODD for values 0-4 (DRAM_REGION_SIZE_ODD) |
| 65 | * -- GET_DRAM_REGION_SIZE_EVEN for values 7-26 (DRAM_REGION_SIZE_EVEN) |
| 66 | * using mentioned formulas we cover whole mapping between "Area length" value |
| 67 | * and real size (see above mapping). |
| 68 | */ |
| 69 | #define DRAM_REGION_SIZE_EVEN(C) (((C) >= 7) && ((C) <= 26)) |
| 70 | #define GET_DRAM_REGION_SIZE_EVEN(C) ((uint64_t)1 << ((C) + 16)) |
| 71 | #define DRAM_REGION_SIZE_ODD(C) ((C) <= 4) |
| 72 | #define GET_DRAM_REGION_SIZE_ODD(C) ((uint64_t)0x18000000 << (C)) |
| 73 | |
| 74 | |
| 75 | uint64_t mvebu_get_dram_size(uint64_t ap_base_addr) |
| 76 | { |
| 77 | uint64_t mem_size = 0; |
| 78 | uint8_t region_code; |
| 79 | uint8_t cs, iface; |
| 80 | |
| 81 | for (iface = 0; iface < DRAM_MAX_IFACE; iface++) { |
| 82 | for (cs = 0; cs < DRAM_MAX_CS_NUM; cs++) { |
| 83 | |
| 84 | /* Exit loop on first disabled DRAM CS */ |
| 85 | if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr)) |
| 86 | break; |
| 87 | |
| 88 | /* Decode area length for current CS |
| 89 | * from register value |
| 90 | */ |
| 91 | region_code = |
| 92 | GET_DRAM_REGION_SIZE_CODE(iface, cs, |
| 93 | ap_base_addr); |
| 94 | |
| 95 | if (DRAM_REGION_SIZE_EVEN(region_code)) { |
| 96 | mem_size += |
| 97 | GET_DRAM_REGION_SIZE_EVEN(region_code); |
| 98 | } else if (DRAM_REGION_SIZE_ODD(region_code)) { |
| 99 | mem_size += |
| 100 | GET_DRAM_REGION_SIZE_ODD(region_code); |
| 101 | } else { |
| 102 | WARN("%s: Invalid mem region (0x%x) CS#%d\n", |
| 103 | __func__, region_code, cs); |
| 104 | return 0; |
| 105 | } |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | return mem_size; |
| 110 | } |