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Soby Mathew7b754182016-07-11 14:15:27 +01001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew7b754182016-07-11 14:15:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew7b754182016-07-11 14:15:27 +01005 */
6
7#include <assert.h>
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +01008#include <bl_common.h>
Soby Mathew7b754182016-07-11 14:15:27 +01009#include <console.h>
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +010010#include <debug.h>
Soby Mathew7b754182016-07-11 14:15:27 +010011#include <mmio.h>
Daniel Boulby05e7f562018-09-19 13:58:20 +010012#include <pl011.h>
Soby Mathew7b754182016-07-11 14:15:27 +010013#include <plat_arm.h>
14#include <platform.h>
15#include <platform_def.h>
16#include <platform_sp_min.h>
17
Soby Mathew7b754182016-07-11 14:15:27 +010018static entry_point_info_t bl33_image_ep_info;
19
20/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7b754182016-07-11 14:15:27 +010021#pragma weak sp_min_platform_setup
22#pragma weak sp_min_plat_arch_setup
Soby Mathew6d07e672018-03-01 10:53:33 +000023#pragma weak plat_arm_sp_min_early_platform_setup
Soby Mathew7b754182016-07-11 14:15:27 +010024
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010025#define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \
26 BL32_BASE, \
27 BL32_END - BL32_BASE, \
28 MT_MEMORY | MT_RW | MT_SECURE)
29
Soby Mathewaf14b462018-06-01 16:53:38 +010030/*
31 * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page
32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
33 */
34CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
Soby Mathew7b754182016-07-11 14:15:27 +010035
36/*******************************************************************************
37 * Return a pointer to the 'entry_point_info' structure of the next image for the
38 * security state specified. BL33 corresponds to the non-secure image type
39 * while BL32 corresponds to the secure image type. A NULL pointer is returned
40 * if the image does not exist.
41 ******************************************************************************/
42entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
43{
44 entry_point_info_t *next_image_info;
45
46 next_image_info = &bl33_image_ep_info;
47
48 /*
49 * None of the images on the ARM development platforms can have 0x0
50 * as the entrypoint
51 */
52 if (next_image_info->pc)
53 return next_image_info;
54 else
55 return NULL;
56}
57
58/*******************************************************************************
Soby Mathew6d07e672018-03-01 10:53:33 +000059 * Utility function to perform early platform setup.
Soby Mathew7b754182016-07-11 14:15:27 +010060 ******************************************************************************/
Soby Mathew7d5a2e72018-01-10 15:59:31 +000061void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
62 uintptr_t hw_config, void *plat_params_from_bl2)
Soby Mathew7b754182016-07-11 14:15:27 +010063{
64 /* Initialize the console to provide early debug support */
Daniel Boulby05e7f562018-09-19 13:58:20 +010065 arm_console_boot_init();
Soby Mathew7b754182016-07-11 14:15:27 +010066
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +010067#if RESET_TO_SP_MIN
68 /* There are no parameters from BL2 if SP_MIN is a reset vector */
69 assert(from_bl2 == NULL);
70 assert(plat_params_from_bl2 == NULL);
71
Soby Mathew7b754182016-07-11 14:15:27 +010072 /* Populate entry point information for BL33 */
73 SET_PARAM_HEAD(&bl33_image_ep_info,
74 PARAM_EP,
75 VERSION_1,
76 0);
77 /*
78 * Tell SP_MIN where the non-trusted software image
79 * is located and the entry state information
80 */
Soby Mathew7b754182016-07-11 14:15:27 +010081 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew7b754182016-07-11 14:15:27 +010082 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +010084
Manish Pandey37c4ec22018-11-02 13:28:25 +000085# if ARM_LINUX_KERNEL_AS_BL33
86 /*
87 * According to the file ``Documentation/arm/Booting`` of the Linux
88 * kernel tree, Linux expects:
89 * r0 = 0
90 * r1 = machine type number, optional in DT-only platforms (~0 if so)
91 * r2 = Physical address of the device tree blob
92 */
93 bl33_image_ep_info.args.arg0 = 0U;
94 bl33_image_ep_info.args.arg1 = ~0U;
95 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE;
96# endif
97
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +010098#else /* RESET_TO_SP_MIN */
99
100 /*
101 * Check params passed from BL2 should not be NULL,
102 */
103 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
104 assert(params_from_bl2 != NULL);
105 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
106 assert(params_from_bl2->h.version >= VERSION_2);
107
108 bl_params_node_t *bl_params = params_from_bl2->head;
109
110 /*
111 * Copy BL33 entry point information.
112 * They are stored in Secure RAM, in BL2's address space.
113 */
114 while (bl_params) {
115 if (bl_params->image_id == BL33_IMAGE_ID) {
116 bl33_image_ep_info = *bl_params->ep_info;
117 break;
118 }
119
120 bl_params = bl_params->next_params_info;
121 }
122
123 if (bl33_image_ep_info.pc == 0)
124 panic();
125
126#endif /* RESET_TO_SP_MIN */
127
Soby Mathew7b754182016-07-11 14:15:27 +0100128}
129
Soby Mathew6d07e672018-03-01 10:53:33 +0000130/*******************************************************************************
131 * Default implementation for sp_min_platform_setup2() for ARM platforms
132 ******************************************************************************/
133void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000134 u_register_t arg2, u_register_t arg3)
Soby Mathew7b754182016-07-11 14:15:27 +0100135{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000136 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Soby Mathew7b754182016-07-11 14:15:27 +0100137
138 /*
139 * Initialize Interconnect for this cluster during cold boot.
140 * No need for locks as no other CPU is active.
141 */
142 plat_arm_interconnect_init();
143
144 /*
145 * Enable Interconnect coherency for the primary CPU's cluster.
146 * Earlier bootloader stages might already do this (e.g. Trusted
147 * Firmware's BL1 does it) but we can't assume so. There is no harm in
148 * executing this code twice anyway.
149 * Platform specific PSCI code will enable coherency for other
150 * clusters.
151 */
152 plat_arm_interconnect_enter_coherency();
153}
154
Soby Mathew6d07e672018-03-01 10:53:33 +0000155void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
156 u_register_t arg2, u_register_t arg3)
157{
158 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
159}
160
Soby Mathew7b754182016-07-11 14:15:27 +0100161/*******************************************************************************
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100162 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit.
163 * Common to ARM standard platforms.
164 ******************************************************************************/
165void arm_sp_min_plat_runtime_setup(void)
166{
167 /* Initialize the runtime console */
Daniel Boulby05e7f562018-09-19 13:58:20 +0100168 arm_console_runtime_init();
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100169}
170
171/*******************************************************************************
Soby Mathew7b754182016-07-11 14:15:27 +0100172 * Perform platform specific setup for SP_MIN
173 ******************************************************************************/
174void sp_min_platform_setup(void)
175{
176 /* Initialize the GIC driver, cpu and distributor interfaces */
177 plat_arm_gic_driver_init();
178 plat_arm_gic_init();
179
180 /*
181 * Do initial security configuration to allow DRAM/device access
182 * (if earlier BL has not already done so).
Soby Mathew7b754182016-07-11 14:15:27 +0100183 */
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +0100184#if RESET_TO_SP_MIN
Soby Mathew7b754182016-07-11 14:15:27 +0100185 plat_arm_security_setup();
Roberto Vargas550eb082018-01-05 16:00:05 +0000186
187#if defined(PLAT_ARM_MEM_PROT_ADDR)
188 arm_nor_psci_do_dyn_mem_protect();
189#endif /* PLAT_ARM_MEM_PROT_ADDR */
190
Yatharth Kochar1c16a4c2016-06-30 14:50:58 +0100191#endif
Soby Mathew7b754182016-07-11 14:15:27 +0100192
193 /* Enable and initialize the System level generic timer */
194 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100195 CNTCR_FCREQ(0U) | CNTCR_EN);
Soby Mathew7b754182016-07-11 14:15:27 +0100196
197 /* Allow access to the System counter timer module */
198 arm_configure_sys_timer();
199
200 /* Initialize power controller before setting up topology */
201 plat_arm_pwrc_setup();
202}
203
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100204void sp_min_plat_runtime_setup(void)
205{
206 arm_sp_min_plat_runtime_setup();
207}
208
Soby Mathew7b754182016-07-11 14:15:27 +0100209/*******************************************************************************
210 * Perform the very early platform specific architectural setup here. At the
211 * moment this only initializes the MMU
212 ******************************************************************************/
213void sp_min_plat_arch_setup(void)
214{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100215 const mmap_region_t bl_regions[] = {
216 MAP_BL_SP_MIN_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100217 ARM_MAP_BL_RO,
Soby Mathew7b754182016-07-11 14:15:27 +0100218#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100219 ARM_MAP_BL_COHERENT_RAM,
Soby Mathew7b754182016-07-11 14:15:27 +0100220#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100221 {0}
222 };
223
Roberto Vargas344ff022018-10-19 16:44:18 +0100224 setup_page_tables(bl_regions, plat_arm_get_mmap());
Soby Mathew7b754182016-07-11 14:15:27 +0100225
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100226 enable_mmu_svc_mon(0);
Soby Mathew7b754182016-07-11 14:15:27 +0100227}