blob: c27de8295d73894c8fe81649a2e2671de4ee1e6b [file] [log] [blame]
developer65014b82015-04-13 14:47:57 +08001/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
developer65014b82015-04-13 14:47:57 +08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer65014b82015-04-13 14:47:57 +08005 */
developer65014b82015-04-13 14:47:57 +08006#include <assert.h>
7#include <bl_common.h>
Masahiro Yamada0fac5af2016-12-28 16:11:41 +09008#include <common_def.h>
developer65014b82015-04-13 14:47:57 +08009#include <console.h>
10#include <debug.h>
Antonio Nino Diaz02a09af2016-05-05 15:23:56 +010011#include <generic_delay_timer.h>
developer65014b82015-04-13 14:47:57 +080012#include <mcucfg.h>
13#include <mmio.h>
14#include <mtcmos.h>
Antonio Nino Diaz42eef852018-09-24 17:15:54 +010015#include <mtk_plat_common.h>
Koan-Sin Tan1d2b6392016-04-18 15:17:57 +080016#include <plat_arm.h>
developer65014b82015-04-13 14:47:57 +080017#include <plat_private.h>
18#include <platform.h>
19#include <spm.h>
20
developer65014b82015-04-13 14:47:57 +080021static entry_point_info_t bl32_ep_info;
22static entry_point_info_t bl33_ep_info;
23
24static void platform_setup_cpu(void)
25{
26 /* turn off all the little core's power except cpu 0 */
27 mtcmos_little_cpu_off();
28
29 /* setup big cores */
30 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res,
31 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
32 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
33 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
34 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
35 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
36 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
37 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
38 MP1_SW_CG_GEN);
39 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
40 MP1_L2RSTDISABLE);
41
42 /* set big cores arm64 boot mode */
43 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
44 MP1_CPUCFG_64BIT);
45
46 /* set LITTLE cores arm64 boot mode */
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
48 MP0_CPUCFG_64BIT);
developer53719632015-11-16 14:18:36 +080049
50 /* enable dcm control */
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl,
52 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN |
53 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN |
54 INFRACLK_PSYS_DYNAMIC_CG_EN);
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl,
56 L2C_SRAM_DCM_EN);
57 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl,
58 MCU_BUS_DCM_EN);
developer65014b82015-04-13 14:47:57 +080059}
60
developer89ddad12016-03-29 17:42:41 +080061static void platform_setup_sram(void)
62{
63 /* protect BL31 memory from non-secure read/write access */
64 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00);
65 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9);
66}
67
developer65014b82015-04-13 14:47:57 +080068/*******************************************************************************
69 * Return a pointer to the 'entry_point_info' structure of the next image for
70 * the security state specified. BL33 corresponds to the non-secure image type
71 * while BL32 corresponds to the secure image type. A NULL pointer is returned
72 * if the image does not exist.
73 ******************************************************************************/
74entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
75{
76 entry_point_info_t *next_image_info;
77
78 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
79
80 /* None of the images on this platform can have 0x0 as the entrypoint */
81 if (next_image_info->pc)
82 return next_image_info;
83 else
84 return NULL;
85}
86
87/*******************************************************************************
88 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010089 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
developer65014b82015-04-13 14:47:57 +080090 * are lost (potentially). This needs to be done before the MMU is initialized
91 * so that the memory layout can be used while creating page tables.
92 * BL2 has flushed this information to memory, so we are guaranteed to pick up
93 * good data.
94 ******************************************************************************/
Antonio Nino Diaz42eef852018-09-24 17:15:54 +010095void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
96 u_register_t arg2, u_register_t arg3)
developer65014b82015-04-13 14:47:57 +080097{
Antonio Nino Diaz42eef852018-09-24 17:15:54 +010098 struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
99
developer65014b82015-04-13 14:47:57 +0800100 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
101
102 VERBOSE("bl31_setup\n");
103
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100104 assert(arg_from_bl2 != NULL);
105 assert(arg_from_bl2->h.type == PARAM_BL31);
106 assert(arg_from_bl2->h.version >= VERSION_1);
developer65014b82015-04-13 14:47:57 +0800107
Antonio Nino Diaz42eef852018-09-24 17:15:54 +0100108 bl32_ep_info = *arg_from_bl2->bl32_ep_info;
109 bl33_ep_info = *arg_from_bl2->bl33_ep_info;
developer65014b82015-04-13 14:47:57 +0800110}
111
112/*******************************************************************************
113 * Perform any BL3-1 platform setup code
114 ******************************************************************************/
115void bl31_platform_setup(void)
116{
117 platform_setup_cpu();
developer89ddad12016-03-29 17:42:41 +0800118 platform_setup_sram();
developer65014b82015-04-13 14:47:57 +0800119
Antonio Nino Diaz02a09af2016-05-05 15:23:56 +0100120 generic_delay_timer_init();
developer65014b82015-04-13 14:47:57 +0800121
122 /* Initialize the gic cpu and distributor interfaces */
Koan-Sin Tan1d2b6392016-04-18 15:17:57 +0800123 plat_arm_gic_driver_init();
124 plat_arm_gic_init();
developer65014b82015-04-13 14:47:57 +0800125
developer65014b82015-04-13 14:47:57 +0800126 /* Initialize spm at boot time */
127 spm_boot_init();
128}
129
130/*******************************************************************************
131 * Perform the very early platform specific architectural setup here. At the
132 * moment this is only intializes the mmu in a quick and dirty way.
133 ******************************************************************************/
134void bl31_plat_arch_setup(void)
135{
136 plat_cci_init();
137 plat_cci_enable();
138
Joel Hutton5cc3bc82018-03-21 11:40:57 +0000139 plat_configure_mmu_el3(BL_CODE_BASE,
140 BL_COHERENT_RAM_END - BL_CODE_BASE,
141 BL_CODE_BASE,
142 BL_CODE_END,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900143 BL_COHERENT_RAM_BASE,
144 BL_COHERENT_RAM_END);
developer65014b82015-04-13 14:47:57 +0800145}
146