| Haojian Zhuang | 5f281b3 | 2017-05-24 08:45:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __HI6220_REGS_PMCTRL_H__ |
| 8 | #define __HI6220_REGS_PMCTRL_H__ |
| 9 | |
| 10 | #define PMCTRL_BASE 0xF7032000 |
| 11 | |
| 12 | #define PMCTRL_ACPUPLLCTRL (PMCTRL_BASE + 0x000) |
| 13 | #define PMCTRL_ACPUPLLFREQ (PMCTRL_BASE + 0x004) |
| 14 | #define PMCTRL_DDRPLL1CTRL (PMCTRL_BASE + 0x010) |
| 15 | #define PMCTRL_DDRPLL0CTRL (PMCTRL_BASE + 0x030) |
| 16 | #define PMCTRL_MEDPLLCTRL (PMCTRL_BASE + 0x038) |
| 17 | #define PMCTRL_ACPUPLLSEL (PMCTRL_BASE + 0x100) |
| 18 | #define PMCTRL_ACPUCLKDIV (PMCTRL_BASE + 0x104) |
| 19 | #define PMCTRL_ACPUSYSPLLCFG (PMCTRL_BASE + 0x110) |
| 20 | #define PMCTRL_ACPUCLKOFFCFG (PMCTRL_BASE + 0x114) |
| 21 | #define PMCTRL_ACPUPLLFRAC (PMCTRL_BASE + 0x134) |
| 22 | #define PMCTRL_ACPUPMUVOLUPTIME (PMCTRL_BASE + 0x360) |
| 23 | #define PMCTRL_ACPUPMUVOLDNTIME (PMCTRL_BASE + 0x364) |
| 24 | #define PMCTRL_ACPUVOLPMUADDR (PMCTRL_BASE + 0x368) |
| 25 | #define PMCTRL_ACPUVOLUPSTEP (PMCTRL_BASE + 0x36c) |
| 26 | #define PMCTRL_ACPUVOLDNSTEP (PMCTRL_BASE + 0x370) |
| 27 | #define PMCTRL_ACPUDFTVOL (PMCTRL_BASE + 0x374) |
| 28 | #define PMCTRL_ACPUDESTVOL (PMCTRL_BASE + 0x378) |
| 29 | #define PMCTRL_ACPUVOLTTIMEOUT (PMCTRL_BASE + 0x37c) |
| 30 | |
| 31 | #define PMCTRL_ACPUPLLCTRL_EN_CFG (1 << 0) |
| 32 | |
| 33 | #define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK (3 << 0) |
| 34 | #define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK (3 << 8) |
| 35 | #define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK (3 << 16) |
| 36 | #define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK (3 << 24) |
| 37 | |
| 38 | #define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG (1 << 0) |
| 39 | #define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT (1 << 1) |
| 40 | #define PMCTRL_ACPUPLLSEL_SYSPLL_STAT (1 << 2) |
| 41 | |
| 42 | #define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK 0x7 |
| 43 | #define PMCTRL_ACPUSYSPLL_CLKEN_CFG (1 << 4) |
| 44 | #define PMCTRL_ACPUSYSPLL_CLKDIV_SW (3 << 12) |
| 45 | |
| 46 | #define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN (1 << 4) |
| 47 | #define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK (3 << 12) |
| 48 | |
| 49 | #define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK 0x7f |
| 50 | #define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK (0x7f << 8) |
| 51 | |
| 52 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START (0) |
| 53 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_END (0) |
| 54 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_START (2) |
| 55 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_END (2) |
| 56 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_START (4) |
| 57 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_END (27) |
| 58 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START (28) |
| 59 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_END (28) |
| 60 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_START (29) |
| 61 | #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_END (29) |
| 62 | |
| 63 | #define SOC_PMCTRL_ACPUPLLFRAC_ADDR(base) ((base) + (0x134)) |
| 64 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START (12) |
| 65 | |
| 66 | #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START (0) |
| 67 | #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_END (0) |
| 68 | #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START (1) |
| 69 | #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_END (1) |
| 70 | #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START (2) |
| 71 | #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_END (2) |
| 72 | |
| 73 | #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START (0) |
| 74 | #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_END (1) |
| 75 | #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START (8) |
| 76 | #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_END (9) |
| 77 | #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START (16) |
| 78 | #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_END (17) |
| 79 | #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START (24) |
| 80 | #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_END (25) |
| 81 | |
| 82 | #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START (0) |
| 83 | #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END (6) |
| 84 | #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START (8) |
| 85 | #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_END (14) |
| 86 | |
| 87 | #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START (0) |
| 88 | #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_END (0) |
| 89 | |
| 90 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_START (0) |
| 91 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_END (2) |
| 92 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START (4) |
| 93 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_END (4) |
| 94 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_START (8) |
| 95 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_END (9) |
| 96 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_START (16) |
| 97 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_END (19) |
| 98 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_START (20) |
| 99 | #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_END (20) |
| 100 | |
| 101 | #endif /* __HI6220_REGS_PMCTRL_H__ */ |