| Javier Almansa Sobrino | e1ecd23 | 2020-08-20 18:48:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <generic.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* --------------------------------------------- |
| 15 | * Disable L1 data cache and unified L2 cache |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func generic_disable_dcache |
| 19 | mrs x1, sctlr_el3 |
| 20 | bic x1, x1, #SCTLR_C_BIT |
| 21 | msr sctlr_el3, x1 |
| 22 | isb |
| 23 | ret |
| 24 | endfunc generic_disable_dcache |
| 25 | |
| 26 | func generic_core_pwr_dwn |
| 27 | mov x18, x30 |
| 28 | |
| 29 | /* --------------------------------------------- |
| 30 | * Turn off caches. |
| 31 | * --------------------------------------------- |
| 32 | */ |
| 33 | bl generic_disable_dcache |
| 34 | |
| 35 | /* --------------------------------------------- |
| 36 | * Flush L1 caches. |
| 37 | * --------------------------------------------- |
| 38 | */ |
| 39 | mov x0, #DCCISW |
| 40 | bl dcsw_op_level1 |
| 41 | |
| 42 | ret x18 |
| 43 | endfunc generic_core_pwr_dwn |
| 44 | |
| 45 | func generic_cluster_pwr_dwn |
| 46 | mov x18, x30 |
| 47 | |
| 48 | /* --------------------------------------------- |
| 49 | * Turn off caches. |
| 50 | * --------------------------------------------- |
| 51 | */ |
| 52 | bl generic_disable_dcache |
| 53 | |
| 54 | /* --------------------------------------------- |
| 55 | * Flush L1 caches. |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | mov x0, #DCCISW |
| 59 | bl dcsw_op_level1 |
| 60 | |
| 61 | /* --------------------------------------------- |
| 62 | * Disable the optional ACP. |
| 63 | * --------------------------------------------- |
| 64 | */ |
| 65 | bl plat_disable_acp |
| 66 | |
| 67 | /* --------------------------------------------- |
| 68 | * Flush L2 caches. |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | mov x0, #DCCISW |
| 72 | bl dcsw_op_level2 |
| 73 | |
| 74 | ret x18 |
| 75 | |
| 76 | endfunc generic_cluster_pwr_dwn |
| 77 | |
| 78 | /* --------------------------------------------- |
| 79 | * Unimplemented functions. |
| 80 | * --------------------------------------------- |
| 81 | */ |
| 82 | .equ generic_errata_report, 0 |
| 83 | .equ generic_cpu_reg_dump, 0 |
| 84 | .equ generic_reset_func, 0 |
| 85 | |
| 86 | declare_cpu_ops generic, AARCH64_GENERIC_MIDR, \ |
| 87 | generic_reset_func, \ |
| 88 | generic_core_pwr_dwn, \ |
| 89 | generic_cluster_pwr_dwn |