| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
| Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef SMMU_H |
| 8 | #define SMMU_H |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/mmio.h> |
| 11 | |
| Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 12 | #include <memctrl_v2.h> |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 13 | #include <tegra_def.h> |
| 14 | |
| 15 | /******************************************************************************* |
| 16 | * SMMU Register constants |
| 17 | ******************************************************************************/ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 18 | #define SMMU_CBn_SCTLR (0x0U) |
| 19 | #define SMMU_CBn_SCTLR_STAGE2 (0x0U) |
| 20 | #define SMMU_CBn_ACTLR (0x4U) |
| 21 | #define SMMU_CBn_RESUME (0x8U) |
| 22 | #define SMMU_CBn_TCR2 (0x10U) |
| 23 | #define SMMU_CBn_TTBR0_LO (0x20U) |
| 24 | #define SMMU_CBn_TTBR0_HI (0x24U) |
| 25 | #define SMMU_CBn_TTBR1_LO (0x28U) |
| 26 | #define SMMU_CBn_TTBR1_HI (0x2cU) |
| 27 | #define SMMU_CBn_TCR_LPAE (0x30U) |
| 28 | #define SMMU_CBn_TCR (0x30U) |
| 29 | #define SMMU_CBn_TCR_EAE_1 (0x30U) |
| 30 | #define SMMU_CBn_TCR (0x30U) |
| 31 | #define SMMU_CBn_CONTEXTIDR (0x34U) |
| 32 | #define SMMU_CBn_CONTEXTIDR_EAE_1 (0x34U) |
| 33 | #define SMMU_CBn_PRRR_MAIR0 (0x38U) |
| 34 | #define SMMU_CBn_NMRR_MAIR1 (0x3cU) |
| 35 | #define SMMU_CBn_SMMU_CBn_PAR (0x50U) |
| 36 | #define SMMU_CBn_SMMU_CBn_PAR0 (0x50U) |
| 37 | #define SMMU_CBn_SMMU_CBn_PAR1 (0x54U) |
| 38 | /* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x50U) */ |
| 39 | /* SMMU_CBn_SMMU_CBn_PAR0_Fault (0x54U) */ |
| 40 | #define SMMU_CBn_FSR (0x58U) |
| 41 | #define SMMU_CBn_FSRRESTORE (0x5cU) |
| 42 | #define SMMU_CBn_FAR_LO (0x60U) |
| 43 | #define SMMU_CBn_FAR_HI (0x64U) |
| 44 | #define SMMU_CBn_FSYNR0 (0x68U) |
| 45 | #define SMMU_CBn_IPAFAR_LO (0x70U) |
| 46 | #define SMMU_CBn_IPAFAR_HI (0x74U) |
| 47 | #define SMMU_CBn_TLBIVA_LO (0x600U) |
| 48 | #define SMMU_CBn_TLBIVA_HI (0x604U) |
| 49 | #define SMMU_CBn_TLBIVA_AARCH_32 (0x600U) |
| 50 | #define SMMU_CBn_TLBIVAA_LO (0x608U) |
| 51 | #define SMMU_CBn_TLBIVAA_HI (0x60cU) |
| 52 | #define SMMU_CBn_TLBIVAA_AARCH_32 (0x608U) |
| 53 | #define SMMU_CBn_TLBIASID (0x610U) |
| 54 | #define SMMU_CBn_TLBIALL (0x618U) |
| 55 | #define SMMU_CBn_TLBIVAL_LO (0x620U) |
| 56 | #define SMMU_CBn_TLBIVAL_HI (0x624U) |
| 57 | #define SMMU_CBn_TLBIVAL_AARCH_32 (0x618U) |
| 58 | #define SMMU_CBn_TLBIVAAL_LO (0x628U) |
| 59 | #define SMMU_CBn_TLBIVAAL_HI (0x62cU) |
| 60 | #define SMMU_CBn_TLBIVAAL_AARCH_32 (0x628U) |
| 61 | #define SMMU_CBn_TLBIIPAS2_LO (0x630U) |
| 62 | #define SMMU_CBn_TLBIIPAS2_HI (0x634U) |
| 63 | #define SMMU_CBn_TLBIIPAS2L_LO (0x638U) |
| 64 | #define SMMU_CBn_TLBIIPAS2L_HI (0x63cU) |
| 65 | #define SMMU_CBn_TLBSYNC (0x7f0U) |
| 66 | #define SMMU_CBn_TLBSTATUS (0x7f4U) |
| 67 | #define SMMU_CBn_ATSR (0x800U) |
| 68 | #define SMMU_CBn_PMEVCNTR0 (0xe00U) |
| 69 | #define SMMU_CBn_PMEVCNTR1 (0xe04U) |
| 70 | #define SMMU_CBn_PMEVCNTR2 (0xe08U) |
| 71 | #define SMMU_CBn_PMEVCNTR3 (0xe0cU) |
| 72 | #define SMMU_CBn_PMEVTYPER0 (0xe80U) |
| 73 | #define SMMU_CBn_PMEVTYPER1 (0xe84U) |
| 74 | #define SMMU_CBn_PMEVTYPER2 (0xe88U) |
| 75 | #define SMMU_CBn_PMEVTYPER3 (0xe8cU) |
| 76 | #define SMMU_CBn_PMCFGR (0xf00U) |
| 77 | #define SMMU_CBn_PMCR (0xf04U) |
| 78 | #define SMMU_CBn_PMCEID (0xf20U) |
| 79 | #define SMMU_CBn_PMCNTENSE (0xf40U) |
| 80 | #define SMMU_CBn_PMCNTENCLR (0xf44U) |
| 81 | #define SMMU_CBn_PMCNTENSET (0xf48U) |
| 82 | #define SMMU_CBn_PMINTENCLR (0xf4cU) |
| 83 | #define SMMU_CBn_PMOVSCLR (0xf50U) |
| 84 | #define SMMU_CBn_PMOVSSET (0xf58U) |
| 85 | #define SMMU_CBn_PMAUTHSTATUS (0xfb8U) |
| 86 | #define SMMU_GNSR0_CR0 (0x0U) |
| 87 | #define SMMU_GNSR0_CR2 (0x8U) |
| 88 | #define SMMU_GNSR0_ACR (0x10U) |
| 89 | #define SMMU_GNSR0_IDR0 (0x20U) |
| 90 | #define SMMU_GNSR0_IDR1 (0x24U) |
| 91 | #define SMMU_GNSR0_IDR2 (0x28U) |
| 92 | #define SMMU_GNSR0_IDR7 (0x3cU) |
| 93 | #define SMMU_GNSR0_GFAR_LO (0x40U) |
| 94 | #define SMMU_GNSR0_GFAR_HI (0x44U) |
| 95 | #define SMMU_GNSR0_GFSR (0x48U) |
| 96 | #define SMMU_GNSR0_GFSRRESTORE (0x4cU) |
| 97 | #define SMMU_GNSR0_GFSYNR0 (0x50U) |
| 98 | #define SMMU_GNSR0_GFSYNR1 (0x54U) |
| 99 | #define SMMU_GNSR0_GFSYNR1_v2 (0x54U) |
| 100 | #define SMMU_GNSR0_TLBIVMID (0x64U) |
| 101 | #define SMMU_GNSR0_TLBIALLNSNH (0x68U) |
| 102 | #define SMMU_GNSR0_TLBIALLH (0x6cU) |
| 103 | #define SMMU_GNSR0_TLBGSYNC (0x70U) |
| 104 | #define SMMU_GNSR0_TLBGSTATUS (0x74U) |
| 105 | #define SMMU_GNSR0_TLBIVAH_LO (0x78U) |
| 106 | #define SMMU_GNSR0_TLBIVALH64_LO (0xb0U) |
| 107 | #define SMMU_GNSR0_TLBIVALH64_HI (0xb4U) |
| 108 | #define SMMU_GNSR0_TLBIVMIDS1 (0xb8U) |
| 109 | #define SMMU_GNSR0_TLBIVAH64_LO (0xc0U) |
| 110 | #define SMMU_GNSR0_TLBIVAH64_HI (0xc4U) |
| 111 | #define SMMU_GNSR0_SMR0 (0x800U) |
| 112 | #define SMMU_GNSR0_SMRn (0x800U) |
| 113 | #define SMMU_GNSR0_SMR1 (0x804U) |
| 114 | #define SMMU_GNSR0_SMR2 (0x808U) |
| 115 | #define SMMU_GNSR0_SMR3 (0x80cU) |
| 116 | #define SMMU_GNSR0_SMR4 (0x810U) |
| 117 | #define SMMU_GNSR0_SMR5 (0x814U) |
| 118 | #define SMMU_GNSR0_SMR6 (0x818U) |
| 119 | #define SMMU_GNSR0_SMR7 (0x81cU) |
| 120 | #define SMMU_GNSR0_SMR8 (0x820U) |
| 121 | #define SMMU_GNSR0_SMR9 (0x824U) |
| 122 | #define SMMU_GNSR0_SMR10 (0x828U) |
| 123 | #define SMMU_GNSR0_SMR11 (0x82cU) |
| 124 | #define SMMU_GNSR0_SMR12 (0x830U) |
| 125 | #define SMMU_GNSR0_SMR13 (0x834U) |
| 126 | #define SMMU_GNSR0_SMR14 (0x838U) |
| 127 | #define SMMU_GNSR0_SMR15 (0x83cU) |
| 128 | #define SMMU_GNSR0_SMR16 (0x840U) |
| 129 | #define SMMU_GNSR0_SMR17 (0x844U) |
| 130 | #define SMMU_GNSR0_SMR18 (0x848U) |
| 131 | #define SMMU_GNSR0_SMR19 (0x84cU) |
| 132 | #define SMMU_GNSR0_SMR20 (0x850U) |
| 133 | #define SMMU_GNSR0_SMR21 (0x854U) |
| 134 | #define SMMU_GNSR0_SMR22 (0x858U) |
| 135 | #define SMMU_GNSR0_SMR23 (0x85cU) |
| 136 | #define SMMU_GNSR0_SMR24 (0x860U) |
| 137 | #define SMMU_GNSR0_SMR25 (0x864U) |
| 138 | #define SMMU_GNSR0_SMR26 (0x868U) |
| 139 | #define SMMU_GNSR0_SMR27 (0x86cU) |
| 140 | #define SMMU_GNSR0_SMR28 (0x870U) |
| 141 | #define SMMU_GNSR0_SMR29 (0x874U) |
| 142 | #define SMMU_GNSR0_SMR30 (0x878U) |
| 143 | #define SMMU_GNSR0_SMR31 (0x87cU) |
| 144 | #define SMMU_GNSR0_SMR32 (0x880U) |
| 145 | #define SMMU_GNSR0_SMR33 (0x884U) |
| 146 | #define SMMU_GNSR0_SMR34 (0x888U) |
| 147 | #define SMMU_GNSR0_SMR35 (0x88cU) |
| 148 | #define SMMU_GNSR0_SMR36 (0x890U) |
| 149 | #define SMMU_GNSR0_SMR37 (0x894U) |
| 150 | #define SMMU_GNSR0_SMR38 (0x898U) |
| 151 | #define SMMU_GNSR0_SMR39 (0x89cU) |
| 152 | #define SMMU_GNSR0_SMR40 (0x8a0U) |
| 153 | #define SMMU_GNSR0_SMR41 (0x8a4U) |
| 154 | #define SMMU_GNSR0_SMR42 (0x8a8U) |
| 155 | #define SMMU_GNSR0_SMR43 (0x8acU) |
| 156 | #define SMMU_GNSR0_SMR44 (0x8b0U) |
| 157 | #define SMMU_GNSR0_SMR45 (0x8b4U) |
| 158 | #define SMMU_GNSR0_SMR46 (0x8b8U) |
| 159 | #define SMMU_GNSR0_SMR47 (0x8bcU) |
| 160 | #define SMMU_GNSR0_SMR48 (0x8c0U) |
| 161 | #define SMMU_GNSR0_SMR49 (0x8c4U) |
| 162 | #define SMMU_GNSR0_SMR50 (0x8c8U) |
| 163 | #define SMMU_GNSR0_SMR51 (0x8ccU) |
| 164 | #define SMMU_GNSR0_SMR52 (0x8d0U) |
| 165 | #define SMMU_GNSR0_SMR53 (0x8d4U) |
| 166 | #define SMMU_GNSR0_SMR54 (0x8d8U) |
| 167 | #define SMMU_GNSR0_SMR55 (0x8dcU) |
| 168 | #define SMMU_GNSR0_SMR56 (0x8e0U) |
| 169 | #define SMMU_GNSR0_SMR57 (0x8e4U) |
| 170 | #define SMMU_GNSR0_SMR58 (0x8e8U) |
| 171 | #define SMMU_GNSR0_SMR59 (0x8ecU) |
| 172 | #define SMMU_GNSR0_SMR60 (0x8f0U) |
| 173 | #define SMMU_GNSR0_SMR61 (0x8f4U) |
| 174 | #define SMMU_GNSR0_SMR62 (0x8f8U) |
| 175 | #define SMMU_GNSR0_SMR63 (0x8fcU) |
| 176 | #define SMMU_GNSR0_SMR64 (0x900U) |
| 177 | #define SMMU_GNSR0_SMR65 (0x904U) |
| 178 | #define SMMU_GNSR0_SMR66 (0x908U) |
| 179 | #define SMMU_GNSR0_SMR67 (0x90cU) |
| 180 | #define SMMU_GNSR0_SMR68 (0x910U) |
| 181 | #define SMMU_GNSR0_SMR69 (0x914U) |
| 182 | #define SMMU_GNSR0_SMR70 (0x918U) |
| 183 | #define SMMU_GNSR0_SMR71 (0x91cU) |
| 184 | #define SMMU_GNSR0_SMR72 (0x920U) |
| 185 | #define SMMU_GNSR0_SMR73 (0x924U) |
| 186 | #define SMMU_GNSR0_SMR74 (0x928U) |
| 187 | #define SMMU_GNSR0_SMR75 (0x92cU) |
| 188 | #define SMMU_GNSR0_SMR76 (0x930U) |
| 189 | #define SMMU_GNSR0_SMR77 (0x934U) |
| 190 | #define SMMU_GNSR0_SMR78 (0x938U) |
| 191 | #define SMMU_GNSR0_SMR79 (0x93cU) |
| 192 | #define SMMU_GNSR0_SMR80 (0x940U) |
| 193 | #define SMMU_GNSR0_SMR81 (0x944U) |
| 194 | #define SMMU_GNSR0_SMR82 (0x948U) |
| 195 | #define SMMU_GNSR0_SMR83 (0x94cU) |
| 196 | #define SMMU_GNSR0_SMR84 (0x950U) |
| 197 | #define SMMU_GNSR0_SMR85 (0x954U) |
| 198 | #define SMMU_GNSR0_SMR86 (0x958U) |
| 199 | #define SMMU_GNSR0_SMR87 (0x95cU) |
| 200 | #define SMMU_GNSR0_SMR88 (0x960U) |
| 201 | #define SMMU_GNSR0_SMR89 (0x964U) |
| 202 | #define SMMU_GNSR0_SMR90 (0x968U) |
| 203 | #define SMMU_GNSR0_SMR91 (0x96cU) |
| 204 | #define SMMU_GNSR0_SMR92 (0x970U) |
| 205 | #define SMMU_GNSR0_SMR93 (0x974U) |
| 206 | #define SMMU_GNSR0_SMR94 (0x978U) |
| 207 | #define SMMU_GNSR0_SMR95 (0x97cU) |
| 208 | #define SMMU_GNSR0_SMR96 (0x980U) |
| 209 | #define SMMU_GNSR0_SMR97 (0x984U) |
| 210 | #define SMMU_GNSR0_SMR98 (0x988U) |
| 211 | #define SMMU_GNSR0_SMR99 (0x98cU) |
| 212 | #define SMMU_GNSR0_SMR100 (0x990U) |
| 213 | #define SMMU_GNSR0_SMR101 (0x994U) |
| 214 | #define SMMU_GNSR0_SMR102 (0x998U) |
| 215 | #define SMMU_GNSR0_SMR103 (0x99cU) |
| 216 | #define SMMU_GNSR0_SMR104 (0x9a0U) |
| 217 | #define SMMU_GNSR0_SMR105 (0x9a4U) |
| 218 | #define SMMU_GNSR0_SMR106 (0x9a8U) |
| 219 | #define SMMU_GNSR0_SMR107 (0x9acU) |
| 220 | #define SMMU_GNSR0_SMR108 (0x9b0U) |
| 221 | #define SMMU_GNSR0_SMR109 (0x9b4U) |
| 222 | #define SMMU_GNSR0_SMR110 (0x9b8U) |
| 223 | #define SMMU_GNSR0_SMR111 (0x9bcU) |
| 224 | #define SMMU_GNSR0_SMR112 (0x9c0U) |
| 225 | #define SMMU_GNSR0_SMR113 (0x9c4U) |
| 226 | #define SMMU_GNSR0_SMR114 (0x9c8U) |
| 227 | #define SMMU_GNSR0_SMR115 (0x9ccU) |
| 228 | #define SMMU_GNSR0_SMR116 (0x9d0U) |
| 229 | #define SMMU_GNSR0_SMR117 (0x9d4U) |
| 230 | #define SMMU_GNSR0_SMR118 (0x9d8U) |
| 231 | #define SMMU_GNSR0_SMR119 (0x9dcU) |
| 232 | #define SMMU_GNSR0_SMR120 (0x9e0U) |
| 233 | #define SMMU_GNSR0_SMR121 (0x9e4U) |
| 234 | #define SMMU_GNSR0_SMR122 (0x9e8U) |
| 235 | #define SMMU_GNSR0_SMR123 (0x9ecU) |
| 236 | #define SMMU_GNSR0_SMR124 (0x9f0U) |
| 237 | #define SMMU_GNSR0_SMR125 (0x9f4U) |
| 238 | #define SMMU_GNSR0_SMR126 (0x9f8U) |
| 239 | #define SMMU_GNSR0_SMR127 (0x9fcU) |
| 240 | #define SMMU_GNSR0_S2CR0 (0xc00U) |
| 241 | #define SMMU_GNSR0_S2CRn (0xc00U) |
| 242 | #define SMMU_GNSR0_S2CRn (0xc00U) |
| 243 | #define SMMU_GNSR0_S2CR1 (0xc04U) |
| 244 | #define SMMU_GNSR0_S2CR2 (0xc08U) |
| 245 | #define SMMU_GNSR0_S2CR3 (0xc0cU) |
| 246 | #define SMMU_GNSR0_S2CR4 (0xc10U) |
| 247 | #define SMMU_GNSR0_S2CR5 (0xc14U) |
| 248 | #define SMMU_GNSR0_S2CR6 (0xc18U) |
| 249 | #define SMMU_GNSR0_S2CR7 (0xc1cU) |
| 250 | #define SMMU_GNSR0_S2CR8 (0xc20U) |
| 251 | #define SMMU_GNSR0_S2CR9 (0xc24U) |
| 252 | #define SMMU_GNSR0_S2CR10 (0xc28U) |
| 253 | #define SMMU_GNSR0_S2CR11 (0xc2cU) |
| 254 | #define SMMU_GNSR0_S2CR12 (0xc30U) |
| 255 | #define SMMU_GNSR0_S2CR13 (0xc34U) |
| 256 | #define SMMU_GNSR0_S2CR14 (0xc38U) |
| 257 | #define SMMU_GNSR0_S2CR15 (0xc3cU) |
| 258 | #define SMMU_GNSR0_S2CR16 (0xc40U) |
| 259 | #define SMMU_GNSR0_S2CR17 (0xc44U) |
| 260 | #define SMMU_GNSR0_S2CR18 (0xc48U) |
| 261 | #define SMMU_GNSR0_S2CR19 (0xc4cU) |
| 262 | #define SMMU_GNSR0_S2CR20 (0xc50U) |
| 263 | #define SMMU_GNSR0_S2CR21 (0xc54U) |
| 264 | #define SMMU_GNSR0_S2CR22 (0xc58U) |
| 265 | #define SMMU_GNSR0_S2CR23 (0xc5cU) |
| 266 | #define SMMU_GNSR0_S2CR24 (0xc60U) |
| 267 | #define SMMU_GNSR0_S2CR25 (0xc64U) |
| 268 | #define SMMU_GNSR0_S2CR26 (0xc68U) |
| 269 | #define SMMU_GNSR0_S2CR27 (0xc6cU) |
| 270 | #define SMMU_GNSR0_S2CR28 (0xc70U) |
| 271 | #define SMMU_GNSR0_S2CR29 (0xc74U) |
| 272 | #define SMMU_GNSR0_S2CR30 (0xc78U) |
| 273 | #define SMMU_GNSR0_S2CR31 (0xc7cU) |
| 274 | #define SMMU_GNSR0_S2CR32 (0xc80U) |
| 275 | #define SMMU_GNSR0_S2CR33 (0xc84U) |
| 276 | #define SMMU_GNSR0_S2CR34 (0xc88U) |
| 277 | #define SMMU_GNSR0_S2CR35 (0xc8cU) |
| 278 | #define SMMU_GNSR0_S2CR36 (0xc90U) |
| 279 | #define SMMU_GNSR0_S2CR37 (0xc94U) |
| 280 | #define SMMU_GNSR0_S2CR38 (0xc98U) |
| 281 | #define SMMU_GNSR0_S2CR39 (0xc9cU) |
| 282 | #define SMMU_GNSR0_S2CR40 (0xca0U) |
| 283 | #define SMMU_GNSR0_S2CR41 (0xca4U) |
| 284 | #define SMMU_GNSR0_S2CR42 (0xca8U) |
| 285 | #define SMMU_GNSR0_S2CR43 (0xcacU) |
| 286 | #define SMMU_GNSR0_S2CR44 (0xcb0U) |
| 287 | #define SMMU_GNSR0_S2CR45 (0xcb4U) |
| 288 | #define SMMU_GNSR0_S2CR46 (0xcb8U) |
| 289 | #define SMMU_GNSR0_S2CR47 (0xcbcU) |
| 290 | #define SMMU_GNSR0_S2CR48 (0xcc0U) |
| 291 | #define SMMU_GNSR0_S2CR49 (0xcc4U) |
| 292 | #define SMMU_GNSR0_S2CR50 (0xcc8U) |
| 293 | #define SMMU_GNSR0_S2CR51 (0xcccU) |
| 294 | #define SMMU_GNSR0_S2CR52 (0xcd0U) |
| 295 | #define SMMU_GNSR0_S2CR53 (0xcd4U) |
| 296 | #define SMMU_GNSR0_S2CR54 (0xcd8U) |
| 297 | #define SMMU_GNSR0_S2CR55 (0xcdcU) |
| 298 | #define SMMU_GNSR0_S2CR56 (0xce0U) |
| 299 | #define SMMU_GNSR0_S2CR57 (0xce4U) |
| 300 | #define SMMU_GNSR0_S2CR58 (0xce8U) |
| 301 | #define SMMU_GNSR0_S2CR59 (0xcecU) |
| 302 | #define SMMU_GNSR0_S2CR60 (0xcf0U) |
| 303 | #define SMMU_GNSR0_S2CR61 (0xcf4U) |
| 304 | #define SMMU_GNSR0_S2CR62 (0xcf8U) |
| 305 | #define SMMU_GNSR0_S2CR63 (0xcfcU) |
| 306 | #define SMMU_GNSR0_S2CR64 (0xd00U) |
| 307 | #define SMMU_GNSR0_S2CR65 (0xd04U) |
| 308 | #define SMMU_GNSR0_S2CR66 (0xd08U) |
| 309 | #define SMMU_GNSR0_S2CR67 (0xd0cU) |
| 310 | #define SMMU_GNSR0_S2CR68 (0xd10U) |
| 311 | #define SMMU_GNSR0_S2CR69 (0xd14U) |
| 312 | #define SMMU_GNSR0_S2CR70 (0xd18U) |
| 313 | #define SMMU_GNSR0_S2CR71 (0xd1cU) |
| 314 | #define SMMU_GNSR0_S2CR72 (0xd20U) |
| 315 | #define SMMU_GNSR0_S2CR73 (0xd24U) |
| 316 | #define SMMU_GNSR0_S2CR74 (0xd28U) |
| 317 | #define SMMU_GNSR0_S2CR75 (0xd2cU) |
| 318 | #define SMMU_GNSR0_S2CR76 (0xd30U) |
| 319 | #define SMMU_GNSR0_S2CR77 (0xd34U) |
| 320 | #define SMMU_GNSR0_S2CR78 (0xd38U) |
| 321 | #define SMMU_GNSR0_S2CR79 (0xd3cU) |
| 322 | #define SMMU_GNSR0_S2CR80 (0xd40U) |
| 323 | #define SMMU_GNSR0_S2CR81 (0xd44U) |
| 324 | #define SMMU_GNSR0_S2CR82 (0xd48U) |
| 325 | #define SMMU_GNSR0_S2CR83 (0xd4cU) |
| 326 | #define SMMU_GNSR0_S2CR84 (0xd50U) |
| 327 | #define SMMU_GNSR0_S2CR85 (0xd54U) |
| 328 | #define SMMU_GNSR0_S2CR86 (0xd58U) |
| 329 | #define SMMU_GNSR0_S2CR87 (0xd5cU) |
| 330 | #define SMMU_GNSR0_S2CR88 (0xd60U) |
| 331 | #define SMMU_GNSR0_S2CR89 (0xd64U) |
| 332 | #define SMMU_GNSR0_S2CR90 (0xd68U) |
| 333 | #define SMMU_GNSR0_S2CR91 (0xd6cU) |
| 334 | #define SMMU_GNSR0_S2CR92 (0xd70U) |
| 335 | #define SMMU_GNSR0_S2CR93 (0xd74U) |
| 336 | #define SMMU_GNSR0_S2CR94 (0xd78U) |
| 337 | #define SMMU_GNSR0_S2CR95 (0xd7cU) |
| 338 | #define SMMU_GNSR0_S2CR96 (0xd80U) |
| 339 | #define SMMU_GNSR0_S2CR97 (0xd84U) |
| 340 | #define SMMU_GNSR0_S2CR98 (0xd88U) |
| 341 | #define SMMU_GNSR0_S2CR99 (0xd8cU) |
| 342 | #define SMMU_GNSR0_S2CR100 (0xd90U) |
| 343 | #define SMMU_GNSR0_S2CR101 (0xd94U) |
| 344 | #define SMMU_GNSR0_S2CR102 (0xd98U) |
| 345 | #define SMMU_GNSR0_S2CR103 (0xd9cU) |
| 346 | #define SMMU_GNSR0_S2CR104 (0xda0U) |
| 347 | #define SMMU_GNSR0_S2CR105 (0xda4U) |
| 348 | #define SMMU_GNSR0_S2CR106 (0xda8U) |
| 349 | #define SMMU_GNSR0_S2CR107 (0xdacU) |
| 350 | #define SMMU_GNSR0_S2CR108 (0xdb0U) |
| 351 | #define SMMU_GNSR0_S2CR109 (0xdb4U) |
| 352 | #define SMMU_GNSR0_S2CR110 (0xdb8U) |
| 353 | #define SMMU_GNSR0_S2CR111 (0xdbcU) |
| 354 | #define SMMU_GNSR0_S2CR112 (0xdc0U) |
| 355 | #define SMMU_GNSR0_S2CR113 (0xdc4U) |
| 356 | #define SMMU_GNSR0_S2CR114 (0xdc8U) |
| 357 | #define SMMU_GNSR0_S2CR115 (0xdccU) |
| 358 | #define SMMU_GNSR0_S2CR116 (0xdd0U) |
| 359 | #define SMMU_GNSR0_S2CR117 (0xdd4U) |
| 360 | #define SMMU_GNSR0_S2CR118 (0xdd8U) |
| 361 | #define SMMU_GNSR0_S2CR119 (0xddcU) |
| 362 | #define SMMU_GNSR0_S2CR120 (0xde0U) |
| 363 | #define SMMU_GNSR0_S2CR121 (0xde4U) |
| 364 | #define SMMU_GNSR0_S2CR122 (0xde8U) |
| 365 | #define SMMU_GNSR0_S2CR123 (0xdecU) |
| 366 | #define SMMU_GNSR0_S2CR124 (0xdf0U) |
| 367 | #define SMMU_GNSR0_S2CR125 (0xdf4U) |
| 368 | #define SMMU_GNSR0_S2CR126 (0xdf8U) |
| 369 | #define SMMU_GNSR0_S2CR127 (0xdfcU) |
| 370 | #define SMMU_GNSR0_PIDR0 (0xfe0U) |
| 371 | #define SMMU_GNSR0_PIDR1 (0xfe4U) |
| 372 | #define SMMU_GNSR0_PIDR2 (0xfe8U) |
| 373 | #define SMMU_GNSR0_PIDR3 (0xfecU) |
| 374 | #define SMMU_GNSR0_PIDR4 (0xfd0U) |
| 375 | #define SMMU_GNSR0_PIDR5 (0xfd4U) |
| 376 | #define SMMU_GNSR0_PIDR6 (0xfd8U) |
| 377 | #define SMMU_GNSR0_PIDR7 (0xfdcU) |
| 378 | #define SMMU_GNSR0_CIDR0 (0xff0U) |
| 379 | #define SMMU_GNSR0_CIDR1 (0xff4U) |
| 380 | #define SMMU_GNSR0_CIDR2 (0xff8U) |
| 381 | #define SMMU_GNSR0_CIDR3 (0xffcU) |
| 382 | #define SMMU_GNSR1_CBAR0 (0x0U) |
| 383 | #define SMMU_GNSR1_CBARn (0x0U) |
| 384 | #define SMMU_GNSR1_CBFRSYNRA0 (0x400U) |
| 385 | #define SMMU_GNSR1_CBA2R0 (0x800U) |
| 386 | #define SMMU_GNSR1_CBAR1 (0x4U) |
| 387 | #define SMMU_GNSR1_CBFRSYNRA1 (0x404U) |
| 388 | #define SMMU_GNSR1_CBA2R1 (0x804U) |
| 389 | #define SMMU_GNSR1_CBAR2 (0x8U) |
| 390 | #define SMMU_GNSR1_CBFRSYNRA2 (0x408U) |
| 391 | #define SMMU_GNSR1_CBA2R2 (0x808U) |
| 392 | #define SMMU_GNSR1_CBAR3 (0xcU) |
| 393 | #define SMMU_GNSR1_CBFRSYNRA3 (0x40cU) |
| 394 | #define SMMU_GNSR1_CBA2R3 (0x80cU) |
| 395 | #define SMMU_GNSR1_CBAR4 (0x10U) |
| 396 | #define SMMU_GNSR1_CBFRSYNRA4 (0x410U) |
| 397 | #define SMMU_GNSR1_CBA2R4 (0x810U) |
| 398 | #define SMMU_GNSR1_CBAR5 (0x14U) |
| 399 | #define SMMU_GNSR1_CBFRSYNRA5 (0x414U) |
| 400 | #define SMMU_GNSR1_CBA2R5 (0x814U) |
| 401 | #define SMMU_GNSR1_CBAR6 (0x18U) |
| 402 | #define SMMU_GNSR1_CBFRSYNRA6 (0x418U) |
| 403 | #define SMMU_GNSR1_CBA2R6 (0x818U) |
| 404 | #define SMMU_GNSR1_CBAR7 (0x1cU) |
| 405 | #define SMMU_GNSR1_CBFRSYNRA7 (0x41cU) |
| 406 | #define SMMU_GNSR1_CBA2R7 (0x81cU) |
| 407 | #define SMMU_GNSR1_CBAR8 (0x20U) |
| 408 | #define SMMU_GNSR1_CBFRSYNRA8 (0x420U) |
| 409 | #define SMMU_GNSR1_CBA2R8 (0x820U) |
| 410 | #define SMMU_GNSR1_CBAR9 (0x24U) |
| 411 | #define SMMU_GNSR1_CBFRSYNRA9 (0x424U) |
| 412 | #define SMMU_GNSR1_CBA2R9 (0x824U) |
| 413 | #define SMMU_GNSR1_CBAR10 (0x28U) |
| 414 | #define SMMU_GNSR1_CBFRSYNRA10 (0x428U) |
| 415 | #define SMMU_GNSR1_CBA2R10 (0x828U) |
| 416 | #define SMMU_GNSR1_CBAR11 (0x2cU) |
| 417 | #define SMMU_GNSR1_CBFRSYNRA11 (0x42cU) |
| 418 | #define SMMU_GNSR1_CBA2R11 (0x82cU) |
| 419 | #define SMMU_GNSR1_CBAR12 (0x30U) |
| 420 | #define SMMU_GNSR1_CBFRSYNRA12 (0x430U) |
| 421 | #define SMMU_GNSR1_CBA2R12 (0x830U) |
| 422 | #define SMMU_GNSR1_CBAR13 (0x34U) |
| 423 | #define SMMU_GNSR1_CBFRSYNRA13 (0x434U) |
| 424 | #define SMMU_GNSR1_CBA2R13 (0x834U) |
| 425 | #define SMMU_GNSR1_CBAR14 (0x38U) |
| 426 | #define SMMU_GNSR1_CBFRSYNRA14 (0x438U) |
| 427 | #define SMMU_GNSR1_CBA2R14 (0x838U) |
| 428 | #define SMMU_GNSR1_CBAR15 (0x3cU) |
| 429 | #define SMMU_GNSR1_CBFRSYNRA15 (0x43cU) |
| 430 | #define SMMU_GNSR1_CBA2R15 (0x83cU) |
| 431 | #define SMMU_GNSR1_CBAR16 (0x40U) |
| 432 | #define SMMU_GNSR1_CBFRSYNRA16 (0x440U) |
| 433 | #define SMMU_GNSR1_CBA2R16 (0x840U) |
| 434 | #define SMMU_GNSR1_CBAR17 (0x44U) |
| 435 | #define SMMU_GNSR1_CBFRSYNRA17 (0x444U) |
| 436 | #define SMMU_GNSR1_CBA2R17 (0x844U) |
| 437 | #define SMMU_GNSR1_CBAR18 (0x48U) |
| 438 | #define SMMU_GNSR1_CBFRSYNRA18 (0x448U) |
| 439 | #define SMMU_GNSR1_CBA2R18 (0x848U) |
| 440 | #define SMMU_GNSR1_CBAR19 (0x4cU) |
| 441 | #define SMMU_GNSR1_CBFRSYNRA19 (0x44cU) |
| 442 | #define SMMU_GNSR1_CBA2R19 (0x84cU) |
| 443 | #define SMMU_GNSR1_CBAR20 (0x50U) |
| 444 | #define SMMU_GNSR1_CBFRSYNRA20 (0x450U) |
| 445 | #define SMMU_GNSR1_CBA2R20 (0x850U) |
| 446 | #define SMMU_GNSR1_CBAR21 (0x54U) |
| 447 | #define SMMU_GNSR1_CBFRSYNRA21 (0x454U) |
| 448 | #define SMMU_GNSR1_CBA2R21 (0x854U) |
| 449 | #define SMMU_GNSR1_CBAR22 (0x58U) |
| 450 | #define SMMU_GNSR1_CBFRSYNRA22 (0x458U) |
| 451 | #define SMMU_GNSR1_CBA2R22 (0x858U) |
| 452 | #define SMMU_GNSR1_CBAR23 (0x5cU) |
| 453 | #define SMMU_GNSR1_CBFRSYNRA23 (0x45cU) |
| 454 | #define SMMU_GNSR1_CBA2R23 (0x85cU) |
| 455 | #define SMMU_GNSR1_CBAR24 (0x60U) |
| 456 | #define SMMU_GNSR1_CBFRSYNRA24 (0x460U) |
| 457 | #define SMMU_GNSR1_CBA2R24 (0x860U) |
| 458 | #define SMMU_GNSR1_CBAR25 (0x64U) |
| 459 | #define SMMU_GNSR1_CBFRSYNRA25 (0x464U) |
| 460 | #define SMMU_GNSR1_CBA2R25 (0x864U) |
| 461 | #define SMMU_GNSR1_CBAR26 (0x68U) |
| 462 | #define SMMU_GNSR1_CBFRSYNRA26 (0x468U) |
| 463 | #define SMMU_GNSR1_CBA2R26 (0x868U) |
| 464 | #define SMMU_GNSR1_CBAR27 (0x6cU) |
| 465 | #define SMMU_GNSR1_CBFRSYNRA27 (0x46cU) |
| 466 | #define SMMU_GNSR1_CBA2R27 (0x86cU) |
| 467 | #define SMMU_GNSR1_CBAR28 (0x70U) |
| 468 | #define SMMU_GNSR1_CBFRSYNRA28 (0x470U) |
| 469 | #define SMMU_GNSR1_CBA2R28 (0x870U) |
| 470 | #define SMMU_GNSR1_CBAR29 (0x74U) |
| 471 | #define SMMU_GNSR1_CBFRSYNRA29 (0x474U) |
| 472 | #define SMMU_GNSR1_CBA2R29 (0x874U) |
| 473 | #define SMMU_GNSR1_CBAR30 (0x78U) |
| 474 | #define SMMU_GNSR1_CBFRSYNRA30 (0x478U) |
| 475 | #define SMMU_GNSR1_CBA2R30 (0x878U) |
| 476 | #define SMMU_GNSR1_CBAR31 (0x7cU) |
| 477 | #define SMMU_GNSR1_CBFRSYNRA31 (0x47cU) |
| 478 | #define SMMU_GNSR1_CBA2R31 (0x87cU) |
| 479 | #define SMMU_GNSR1_CBAR32 (0x80U) |
| 480 | #define SMMU_GNSR1_CBFRSYNRA32 (0x480U) |
| 481 | #define SMMU_GNSR1_CBA2R32 (0x880U) |
| 482 | #define SMMU_GNSR1_CBAR33 (0x84U) |
| 483 | #define SMMU_GNSR1_CBFRSYNRA33 (0x484U) |
| 484 | #define SMMU_GNSR1_CBA2R33 (0x884U) |
| 485 | #define SMMU_GNSR1_CBAR34 (0x88U) |
| 486 | #define SMMU_GNSR1_CBFRSYNRA34 (0x488U) |
| 487 | #define SMMU_GNSR1_CBA2R34 (0x888U) |
| 488 | #define SMMU_GNSR1_CBAR35 (0x8cU) |
| 489 | #define SMMU_GNSR1_CBFRSYNRA35 (0x48cU) |
| 490 | #define SMMU_GNSR1_CBA2R35 (0x88cU) |
| 491 | #define SMMU_GNSR1_CBAR36 (0x90U) |
| 492 | #define SMMU_GNSR1_CBFRSYNRA36 (0x490U) |
| 493 | #define SMMU_GNSR1_CBA2R36 (0x890U) |
| 494 | #define SMMU_GNSR1_CBAR37 (0x94U) |
| 495 | #define SMMU_GNSR1_CBFRSYNRA37 (0x494U) |
| 496 | #define SMMU_GNSR1_CBA2R37 (0x894U) |
| 497 | #define SMMU_GNSR1_CBAR38 (0x98U) |
| 498 | #define SMMU_GNSR1_CBFRSYNRA38 (0x498U) |
| 499 | #define SMMU_GNSR1_CBA2R38 (0x898U) |
| 500 | #define SMMU_GNSR1_CBAR39 (0x9cU) |
| 501 | #define SMMU_GNSR1_CBFRSYNRA39 (0x49cU) |
| 502 | #define SMMU_GNSR1_CBA2R39 (0x89cU) |
| 503 | #define SMMU_GNSR1_CBAR40 (0xa0U) |
| 504 | #define SMMU_GNSR1_CBFRSYNRA40 (0x4a0U) |
| 505 | #define SMMU_GNSR1_CBA2R40 (0x8a0U) |
| 506 | #define SMMU_GNSR1_CBAR41 (0xa4U) |
| 507 | #define SMMU_GNSR1_CBFRSYNRA41 (0x4a4U) |
| 508 | #define SMMU_GNSR1_CBA2R41 (0x8a4U) |
| 509 | #define SMMU_GNSR1_CBAR42 (0xa8U) |
| 510 | #define SMMU_GNSR1_CBFRSYNRA42 (0x4a8U) |
| 511 | #define SMMU_GNSR1_CBA2R42 (0x8a8U) |
| 512 | #define SMMU_GNSR1_CBAR43 (0xacU) |
| 513 | #define SMMU_GNSR1_CBFRSYNRA43 (0x4acU) |
| 514 | #define SMMU_GNSR1_CBA2R43 (0x8acU) |
| 515 | #define SMMU_GNSR1_CBAR44 (0xb0U) |
| 516 | #define SMMU_GNSR1_CBFRSYNRA44 (0x4b0U) |
| 517 | #define SMMU_GNSR1_CBA2R44 (0x8b0U) |
| 518 | #define SMMU_GNSR1_CBAR45 (0xb4U) |
| 519 | #define SMMU_GNSR1_CBFRSYNRA45 (0x4b4U) |
| 520 | #define SMMU_GNSR1_CBA2R45 (0x8b4U) |
| 521 | #define SMMU_GNSR1_CBAR46 (0xb8U) |
| 522 | #define SMMU_GNSR1_CBFRSYNRA46 (0x4b8U) |
| 523 | #define SMMU_GNSR1_CBA2R46 (0x8b8U) |
| 524 | #define SMMU_GNSR1_CBAR47 (0xbcU) |
| 525 | #define SMMU_GNSR1_CBFRSYNRA47 (0x4bcU) |
| 526 | #define SMMU_GNSR1_CBA2R47 (0x8bcU) |
| 527 | #define SMMU_GNSR1_CBAR48 (0xc0U) |
| 528 | #define SMMU_GNSR1_CBFRSYNRA48 (0x4c0U) |
| 529 | #define SMMU_GNSR1_CBA2R48 (0x8c0U) |
| 530 | #define SMMU_GNSR1_CBAR49 (0xc4U) |
| 531 | #define SMMU_GNSR1_CBFRSYNRA49 (0x4c4U) |
| 532 | #define SMMU_GNSR1_CBA2R49 (0x8c4U) |
| 533 | #define SMMU_GNSR1_CBAR50 (0xc8U) |
| 534 | #define SMMU_GNSR1_CBFRSYNRA50 (0x4c8U) |
| 535 | #define SMMU_GNSR1_CBA2R50 (0x8c8U) |
| 536 | #define SMMU_GNSR1_CBAR51 (0xccU) |
| 537 | #define SMMU_GNSR1_CBFRSYNRA51 (0x4ccU) |
| 538 | #define SMMU_GNSR1_CBA2R51 (0x8ccU) |
| 539 | #define SMMU_GNSR1_CBAR52 (0xd0U) |
| 540 | #define SMMU_GNSR1_CBFRSYNRA52 (0x4d0U) |
| 541 | #define SMMU_GNSR1_CBA2R52 (0x8d0U) |
| 542 | #define SMMU_GNSR1_CBAR53 (0xd4U) |
| 543 | #define SMMU_GNSR1_CBFRSYNRA53 (0x4d4U) |
| 544 | #define SMMU_GNSR1_CBA2R53 (0x8d4U) |
| 545 | #define SMMU_GNSR1_CBAR54 (0xd8U) |
| 546 | #define SMMU_GNSR1_CBFRSYNRA54 (0x4d8U) |
| 547 | #define SMMU_GNSR1_CBA2R54 (0x8d8U) |
| 548 | #define SMMU_GNSR1_CBAR55 (0xdcU) |
| 549 | #define SMMU_GNSR1_CBFRSYNRA55 (0x4dcU) |
| 550 | #define SMMU_GNSR1_CBA2R55 (0x8dcU) |
| 551 | #define SMMU_GNSR1_CBAR56 (0xe0U) |
| 552 | #define SMMU_GNSR1_CBFRSYNRA56 (0x4e0U) |
| 553 | #define SMMU_GNSR1_CBA2R56 (0x8e0U) |
| 554 | #define SMMU_GNSR1_CBAR57 (0xe4U) |
| 555 | #define SMMU_GNSR1_CBFRSYNRA57 (0x4e4U) |
| 556 | #define SMMU_GNSR1_CBA2R57 (0x8e4U) |
| 557 | #define SMMU_GNSR1_CBAR58 (0xe8U) |
| 558 | #define SMMU_GNSR1_CBFRSYNRA58 (0x4e8U) |
| 559 | #define SMMU_GNSR1_CBA2R58 (0x8e8U) |
| 560 | #define SMMU_GNSR1_CBAR59 (0xecU) |
| 561 | #define SMMU_GNSR1_CBFRSYNRA59 (0x4ecU) |
| 562 | #define SMMU_GNSR1_CBA2R59 (0x8ecU) |
| 563 | #define SMMU_GNSR1_CBAR60 (0xf0U) |
| 564 | #define SMMU_GNSR1_CBFRSYNRA60 (0x4f0U) |
| 565 | #define SMMU_GNSR1_CBA2R60 (0x8f0U) |
| 566 | #define SMMU_GNSR1_CBAR61 (0xf4U) |
| 567 | #define SMMU_GNSR1_CBFRSYNRA61 (0x4f4U) |
| 568 | #define SMMU_GNSR1_CBA2R61 (0x8f4U) |
| 569 | #define SMMU_GNSR1_CBAR62 (0xf8U) |
| 570 | #define SMMU_GNSR1_CBFRSYNRA62 (0x4f8U) |
| 571 | #define SMMU_GNSR1_CBA2R62 (0x8f8U) |
| 572 | #define SMMU_GNSR1_CBAR63 (0xfcU) |
| 573 | #define SMMU_GNSR1_CBFRSYNRA63 (0x4fcU) |
| 574 | #define SMMU_GNSR1_CBA2R63 (0x8fcU) |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 575 | |
| 576 | /******************************************************************************* |
| 577 | * SMMU Global Secure Aux. Configuration Register |
| 578 | ******************************************************************************/ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 579 | #define SMMU_GSR0_SECURE_ACR 0x10U |
| 580 | #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) |
| 581 | #define SMMU_GSR0_PGSIZE_SHIFT 16U |
| 582 | #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) |
| 583 | #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) |
| 584 | #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1U << 26) |
| Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 585 | |
| 586 | /******************************************************************************* |
| 587 | * SMMU Global Aux. Control Register |
| 588 | ******************************************************************************/ |
| Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 589 | #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 590 | |
| 591 | /******************************************************************************* |
| 592 | * SMMU configuration constants |
| 593 | ******************************************************************************/ |
| Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 594 | #define ID1_PAGESIZE (1U << 31U) |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 595 | #define ID1_NUMPAGENDXB_SHIFT 28U |
| 596 | #define ID1_NUMPAGENDXB_MASK 7U |
| 597 | #define ID1_NUMS2CB_SHIFT 16U |
| 598 | #define ID1_NUMS2CB_MASK 0xffU |
| 599 | #define ID1_NUMCB_SHIFT 0U |
| 600 | #define ID1_NUMCB_MASK 0xffU |
| 601 | #define PGSHIFT 16U |
| 602 | #define CB_SIZE 0x800000U |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 603 | |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 604 | typedef struct smmu_regs { |
| 605 | uint32_t reg; |
| 606 | uint32_t val; |
| 607 | } smmu_regs_t; |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 608 | |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 609 | #define mc_make_sid_override_cfg(name) \ |
| 610 | { \ |
| 611 | .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 612 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | #define mc_make_sid_security_cfg(name) \ |
| 616 | { \ |
| 617 | .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 618 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 619 | } |
| 620 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 621 | #define smmu_make_gnsr0_sec_cfg(base_addr, name) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 622 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 623 | .reg = base_addr + SMMU_GNSR0_ ## name, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 624 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | /* |
| 628 | * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers |
| 629 | * is 0x400. So, add it to register address |
| 630 | */ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 631 | #define smmu_make_gnsr0_nsec_cfg(base_addr, name) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 632 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 633 | .reg = base_addr + 0x400U + SMMU_GNSR0_ ## name, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 634 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 635 | } |
| 636 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 637 | #define smmu_make_gnsr0_smr_cfg(base_addr, n) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 638 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 639 | .reg = base_addr + SMMU_GNSR0_SMR ## n, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 640 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 641 | } |
| 642 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 643 | #define smmu_make_gnsr0_s2cr_cfg(base_addr, n) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 644 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 645 | .reg = base_addr + SMMU_GNSR0_S2CR ## n, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 646 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 647 | } |
| 648 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 649 | #define smmu_make_gnsr1_cbar_cfg(base_addr, n) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 650 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 651 | .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 652 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 653 | } |
| 654 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 655 | #define smmu_make_gnsr1_cba2r_cfg(base_addr, n) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 656 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 657 | .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 658 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 659 | } |
| 660 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 661 | #define smmu_make_cb_cfg(base_addr, name, n) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 662 | { \ |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 663 | .reg = base_addr + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 664 | + SMMU_CBn_ ## name, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 665 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 666 | } |
| 667 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 668 | #define smmu_make_smrg_group(base_addr, n) \ |
| 669 | smmu_make_gnsr0_smr_cfg(base_addr, n), \ |
| 670 | smmu_make_gnsr0_s2cr_cfg(base_addr, n), \ |
| 671 | smmu_make_gnsr1_cbar_cfg(base_addr, n), \ |
| 672 | smmu_make_gnsr1_cba2r_cfg(base_addr, n) /* don't put "," here. */ |
| 673 | |
| 674 | #define smmu_make_cb_group(base_addr, n) \ |
| 675 | smmu_make_cb_cfg(base_addr, SCTLR, n), \ |
| 676 | smmu_make_cb_cfg(base_addr, TCR2, n), \ |
| 677 | smmu_make_cb_cfg(base_addr, TTBR0_LO, n), \ |
| 678 | smmu_make_cb_cfg(base_addr, TTBR0_HI, n), \ |
| 679 | smmu_make_cb_cfg(base_addr, TCR, n), \ |
| 680 | smmu_make_cb_cfg(base_addr, PRRR_MAIR0, n),\ |
| 681 | smmu_make_cb_cfg(base_addr, FSR, n), \ |
| 682 | smmu_make_cb_cfg(base_addr, FAR_LO, n), \ |
| 683 | smmu_make_cb_cfg(base_addr, FAR_HI, n), \ |
| 684 | smmu_make_cb_cfg(base_addr, FSYNR0, n) /* don't put "," here. */ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 685 | |
| Pritesh Raithatha | 2437071 | 2017-10-26 16:59:58 +0530 | [diff] [blame] | 686 | #define smmu_make_cfg(base_addr) \ |
| 687 | smmu_make_gnsr0_nsec_cfg(base_addr, CR0), \ |
| 688 | smmu_make_gnsr0_sec_cfg(base_addr, IDR0), \ |
| 689 | smmu_make_gnsr0_sec_cfg(base_addr, IDR1), \ |
| 690 | smmu_make_gnsr0_sec_cfg(base_addr, IDR2), \ |
| 691 | smmu_make_gnsr0_nsec_cfg(base_addr, GFSR), \ |
| 692 | smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR0), \ |
| 693 | smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR1), \ |
| 694 | smmu_make_gnsr0_nsec_cfg(base_addr, TLBGSTATUS),\ |
| 695 | smmu_make_gnsr0_nsec_cfg(base_addr, PIDR2), \ |
| 696 | smmu_make_smrg_group(base_addr, 0), \ |
| 697 | smmu_make_smrg_group(base_addr, 1), \ |
| 698 | smmu_make_smrg_group(base_addr, 2), \ |
| 699 | smmu_make_smrg_group(base_addr, 3), \ |
| 700 | smmu_make_smrg_group(base_addr, 4), \ |
| 701 | smmu_make_smrg_group(base_addr, 5), \ |
| 702 | smmu_make_smrg_group(base_addr, 6), \ |
| 703 | smmu_make_smrg_group(base_addr, 7), \ |
| 704 | smmu_make_smrg_group(base_addr, 8), \ |
| 705 | smmu_make_smrg_group(base_addr, 9), \ |
| 706 | smmu_make_smrg_group(base_addr, 10), \ |
| 707 | smmu_make_smrg_group(base_addr, 11), \ |
| 708 | smmu_make_smrg_group(base_addr, 12), \ |
| 709 | smmu_make_smrg_group(base_addr, 13), \ |
| 710 | smmu_make_smrg_group(base_addr, 14), \ |
| 711 | smmu_make_smrg_group(base_addr, 15), \ |
| 712 | smmu_make_smrg_group(base_addr, 16), \ |
| 713 | smmu_make_smrg_group(base_addr, 17), \ |
| 714 | smmu_make_smrg_group(base_addr, 18), \ |
| 715 | smmu_make_smrg_group(base_addr, 19), \ |
| 716 | smmu_make_smrg_group(base_addr, 20), \ |
| 717 | smmu_make_smrg_group(base_addr, 21), \ |
| 718 | smmu_make_smrg_group(base_addr, 22), \ |
| 719 | smmu_make_smrg_group(base_addr, 23), \ |
| 720 | smmu_make_smrg_group(base_addr, 24), \ |
| 721 | smmu_make_smrg_group(base_addr, 25), \ |
| 722 | smmu_make_smrg_group(base_addr, 26), \ |
| 723 | smmu_make_smrg_group(base_addr, 27), \ |
| 724 | smmu_make_smrg_group(base_addr, 28), \ |
| 725 | smmu_make_smrg_group(base_addr, 29), \ |
| 726 | smmu_make_smrg_group(base_addr, 30), \ |
| 727 | smmu_make_smrg_group(base_addr, 31), \ |
| 728 | smmu_make_smrg_group(base_addr, 32), \ |
| 729 | smmu_make_smrg_group(base_addr, 33), \ |
| 730 | smmu_make_smrg_group(base_addr, 34), \ |
| 731 | smmu_make_smrg_group(base_addr, 35), \ |
| 732 | smmu_make_smrg_group(base_addr, 36), \ |
| 733 | smmu_make_smrg_group(base_addr, 37), \ |
| 734 | smmu_make_smrg_group(base_addr, 38), \ |
| 735 | smmu_make_smrg_group(base_addr, 39), \ |
| 736 | smmu_make_smrg_group(base_addr, 40), \ |
| 737 | smmu_make_smrg_group(base_addr, 41), \ |
| 738 | smmu_make_smrg_group(base_addr, 42), \ |
| 739 | smmu_make_smrg_group(base_addr, 43), \ |
| 740 | smmu_make_smrg_group(base_addr, 44), \ |
| 741 | smmu_make_smrg_group(base_addr, 45), \ |
| 742 | smmu_make_smrg_group(base_addr, 46), \ |
| 743 | smmu_make_smrg_group(base_addr, 47), \ |
| 744 | smmu_make_smrg_group(base_addr, 48), \ |
| 745 | smmu_make_smrg_group(base_addr, 49), \ |
| 746 | smmu_make_smrg_group(base_addr, 50), \ |
| 747 | smmu_make_smrg_group(base_addr, 51), \ |
| 748 | smmu_make_smrg_group(base_addr, 52), \ |
| 749 | smmu_make_smrg_group(base_addr, 53), \ |
| 750 | smmu_make_smrg_group(base_addr, 54), \ |
| 751 | smmu_make_smrg_group(base_addr, 55), \ |
| 752 | smmu_make_smrg_group(base_addr, 56), \ |
| 753 | smmu_make_smrg_group(base_addr, 57), \ |
| 754 | smmu_make_smrg_group(base_addr, 58), \ |
| 755 | smmu_make_smrg_group(base_addr, 59), \ |
| 756 | smmu_make_smrg_group(base_addr, 60), \ |
| 757 | smmu_make_smrg_group(base_addr, 61), \ |
| 758 | smmu_make_smrg_group(base_addr, 62), \ |
| 759 | smmu_make_smrg_group(base_addr, 63), \ |
| 760 | smmu_make_cb_group(base_addr, 0), \ |
| 761 | smmu_make_cb_group(base_addr, 1), \ |
| 762 | smmu_make_cb_group(base_addr, 2), \ |
| 763 | smmu_make_cb_group(base_addr, 3), \ |
| 764 | smmu_make_cb_group(base_addr, 4), \ |
| 765 | smmu_make_cb_group(base_addr, 5), \ |
| 766 | smmu_make_cb_group(base_addr, 6), \ |
| 767 | smmu_make_cb_group(base_addr, 7), \ |
| 768 | smmu_make_cb_group(base_addr, 8), \ |
| 769 | smmu_make_cb_group(base_addr, 9), \ |
| 770 | smmu_make_cb_group(base_addr, 10), \ |
| 771 | smmu_make_cb_group(base_addr, 11), \ |
| 772 | smmu_make_cb_group(base_addr, 12), \ |
| 773 | smmu_make_cb_group(base_addr, 13), \ |
| 774 | smmu_make_cb_group(base_addr, 14), \ |
| 775 | smmu_make_cb_group(base_addr, 15), \ |
| 776 | smmu_make_cb_group(base_addr, 16), \ |
| 777 | smmu_make_cb_group(base_addr, 17), \ |
| 778 | smmu_make_cb_group(base_addr, 18), \ |
| 779 | smmu_make_cb_group(base_addr, 19), \ |
| 780 | smmu_make_cb_group(base_addr, 20), \ |
| 781 | smmu_make_cb_group(base_addr, 21), \ |
| 782 | smmu_make_cb_group(base_addr, 22), \ |
| 783 | smmu_make_cb_group(base_addr, 23), \ |
| 784 | smmu_make_cb_group(base_addr, 24), \ |
| 785 | smmu_make_cb_group(base_addr, 25), \ |
| 786 | smmu_make_cb_group(base_addr, 26), \ |
| 787 | smmu_make_cb_group(base_addr, 27), \ |
| 788 | smmu_make_cb_group(base_addr, 28), \ |
| 789 | smmu_make_cb_group(base_addr, 29), \ |
| 790 | smmu_make_cb_group(base_addr, 30), \ |
| 791 | smmu_make_cb_group(base_addr, 31), \ |
| 792 | smmu_make_cb_group(base_addr, 32), \ |
| 793 | smmu_make_cb_group(base_addr, 33), \ |
| 794 | smmu_make_cb_group(base_addr, 34), \ |
| 795 | smmu_make_cb_group(base_addr, 35), \ |
| 796 | smmu_make_cb_group(base_addr, 36), \ |
| 797 | smmu_make_cb_group(base_addr, 37), \ |
| 798 | smmu_make_cb_group(base_addr, 38), \ |
| 799 | smmu_make_cb_group(base_addr, 39), \ |
| 800 | smmu_make_cb_group(base_addr, 40), \ |
| 801 | smmu_make_cb_group(base_addr, 41), \ |
| 802 | smmu_make_cb_group(base_addr, 42), \ |
| 803 | smmu_make_cb_group(base_addr, 43), \ |
| 804 | smmu_make_cb_group(base_addr, 44), \ |
| 805 | smmu_make_cb_group(base_addr, 45), \ |
| 806 | smmu_make_cb_group(base_addr, 46), \ |
| 807 | smmu_make_cb_group(base_addr, 47), \ |
| 808 | smmu_make_cb_group(base_addr, 48), \ |
| 809 | smmu_make_cb_group(base_addr, 49), \ |
| 810 | smmu_make_cb_group(base_addr, 50), \ |
| 811 | smmu_make_cb_group(base_addr, 51), \ |
| 812 | smmu_make_cb_group(base_addr, 52), \ |
| 813 | smmu_make_cb_group(base_addr, 53), \ |
| 814 | smmu_make_cb_group(base_addr, 54), \ |
| 815 | smmu_make_cb_group(base_addr, 55), \ |
| 816 | smmu_make_cb_group(base_addr, 56), \ |
| 817 | smmu_make_cb_group(base_addr, 57), \ |
| 818 | smmu_make_cb_group(base_addr, 58), \ |
| 819 | smmu_make_cb_group(base_addr, 59), \ |
| 820 | smmu_make_cb_group(base_addr, 60), \ |
| 821 | smmu_make_cb_group(base_addr, 61), \ |
| 822 | smmu_make_cb_group(base_addr, 62), \ |
| 823 | smmu_make_cb_group(base_addr, 63) /* don't put "," here. */ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 824 | |
| 825 | #define smmu_bypass_cfg \ |
| 826 | { \ |
| 827 | .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 828 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 829 | } |
| 830 | |
| 831 | #define _START_OF_TABLE_ \ |
| 832 | { \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 833 | .reg = 0xCAFE05C7U, \ |
| 834 | .val = 0x00000000U, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | #define _END_OF_TABLE_ \ |
| 838 | { \ |
| Anthony Zhou | 59fd615 | 2017-03-13 15:34:08 +0800 | [diff] [blame] | 839 | .reg = 0xFFFFFFFFU, \ |
| 840 | .val = 0xFFFFFFFFU, \ |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 841 | } |
| 842 | |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 843 | |
| 844 | void tegra_smmu_init(void); |
| Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 845 | void tegra_smmu_save_context(uint64_t smmu_ctx_addr); |
| Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame] | 846 | smmu_regs_t *plat_get_smmu_ctx(void); |
| Steven Kao | 7fd30f5 | 2017-07-25 11:29:46 +0800 | [diff] [blame] | 847 | uint32_t plat_get_num_smmu_devices(void); |
| Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 848 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 849 | #endif /* SMMU_H */ |