blob: 102feb22a65ec0e589acb70e5cfdea7d9835835f [file] [log] [blame]
developer65014b82015-04-13 14:47:57 +08001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer65014b82015-04-13 14:47:57 +08005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
7#include <common/debug.h>
8#include <common/runtime_svc.h>
9#include <lib/mmio.h>
10
developereee29802016-05-11 18:45:20 +080011#include <crypt.h>
developerb8925a22015-11-16 14:38:40 +080012#include <mtcmos.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010013#include <mtk_sip_svc.h>
developer73b982f2016-05-11 18:04:09 +080014#include <plat_sip_calls.h>
developer65014b82015-04-13 14:47:57 +080015
16/* Authorized secure register list */
17enum {
18 SREG_HDMI_COLOR_EN = 0x14000904
19};
20
21static const uint32_t authorized_sreg[] = {
22 SREG_HDMI_COLOR_EN
23};
24
25#define authorized_sreg_cnt \
26 (sizeof(authorized_sreg) / sizeof(authorized_sreg[0]))
27
28uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val)
29{
30 uint64_t i;
31
32 for (i = 0; i < authorized_sreg_cnt; i++) {
33 if (authorized_sreg[i] == sreg) {
34 mmio_write_32(sreg, val);
35 return MTK_SIP_E_SUCCESS;
36 }
37 }
38
39 return MTK_SIP_E_INVALID_PARAM;
40}
developerb8925a22015-11-16 14:38:40 +080041
developer73b982f2016-05-11 18:04:09 +080042static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val)
developerb8925a22015-11-16 14:38:40 +080043{
44 uint32_t ret;
45
46 ret = mtcmos_non_cpu_ctrl(1, val);
47 if (ret)
48 return MTK_SIP_E_INVALID_PARAM;
49 else
50 return MTK_SIP_E_SUCCESS;
51}
52
developer73b982f2016-05-11 18:04:09 +080053static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val)
developerb8925a22015-11-16 14:38:40 +080054{
55 uint32_t ret;
56
57 ret = mtcmos_non_cpu_ctrl(0, val);
58 if (ret)
59 return MTK_SIP_E_INVALID_PARAM;
60 else
61 return MTK_SIP_E_SUCCESS;
62}
63
developer73b982f2016-05-11 18:04:09 +080064static uint64_t mt_sip_pwr_mtcmos_support(void)
developerb8925a22015-11-16 14:38:40 +080065{
66 return MTK_SIP_E_SUCCESS;
67}
developer73b982f2016-05-11 18:04:09 +080068
69uint64_t mediatek_plat_sip_handler(uint32_t smc_fid,
70 uint64_t x1,
71 uint64_t x2,
72 uint64_t x3,
73 uint64_t x4,
74 void *cookie,
75 void *handle,
76 uint64_t flags)
77{
78 uint64_t ret;
79
80 switch (smc_fid) {
81 case MTK_SIP_PWR_ON_MTCMOS:
82 ret = mt_sip_pwr_on_mtcmos((uint32_t)x1);
83 SMC_RET1(handle, ret);
84
85 case MTK_SIP_PWR_OFF_MTCMOS:
86 ret = mt_sip_pwr_off_mtcmos((uint32_t)x1);
87 SMC_RET1(handle, ret);
88
89 case MTK_SIP_PWR_MTCMOS_SUPPORT:
90 ret = mt_sip_pwr_mtcmos_support();
91 SMC_RET1(handle, ret);
92
developereee29802016-05-11 18:45:20 +080093 case MTK_SIP_SET_HDCP_KEY_EX:
94 ret = crypt_set_hdcp_key_ex(x1, x2, x3);
95 SMC_RET1(handle, ret);
96
97 case MTK_SIP_SET_HDCP_KEY_NUM:
98 ret = crypt_set_hdcp_key_num((uint32_t)x1);
99 SMC_RET1(handle, ret);
100
101 case MTK_SIP_CLR_HDCP_KEY:
102 ret = crypt_clear_hdcp_key();
103 SMC_RET1(handle, ret);
104
developer73b982f2016-05-11 18:04:09 +0800105 default:
106 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
107 break;
108 }
109
110 SMC_RET1(handle, SMC_UNK);
111}