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Andre Przywara2d42e5f2020-11-28 01:39:17 +00001/*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SUNXI_MMAP_H
8#define SUNXI_MMAP_H
9
10/* Memory regions */
11#define SUNXI_ROM_BASE 0x00000000
12#define SUNXI_ROM_SIZE 0x00010000
13#define SUNXI_SRAM_BASE 0x00020000
14#define SUNXI_SRAM_SIZE 0x00038000
15#define SUNXI_SRAM_A1_BASE 0x00020000
16#define SUNXI_SRAM_A1_SIZE 0x00008000
17#define SUNXI_SRAM_C_BASE 0x00028000
18#define SUNXI_SRAM_C_SIZE 0x00030000
19#define SUNXI_DEV_BASE 0x01000000
20#define SUNXI_DEV_SIZE 0x09000000
21#define SUNXI_DRAM_BASE 0x40000000
22#define SUNXI_DRAM_VIRT_BASE SUNXI_DRAM_BASE
23
24/* Memory-mapped devices */
25#define SUNXI_SYSCON_BASE 0x03000000
26#define SUNXI_CCU_BASE 0x03001000
27#define SUNXI_DMA_BASE 0x03002000
28#define SUNXI_SID_BASE 0x03006000
29#define SUNXI_SPC_BASE 0x03008000
30#define SUNXI_WDOG_BASE 0x030090a0
31#define SUNXI_PIO_BASE 0x0300b000
32#define SUNXI_GICD_BASE 0x03021000
33#define SUNXI_GICC_BASE 0x03022000
34#define SUNXI_UART0_BASE 0x05000000
35#define SUNXI_SPI0_BASE 0x05010000
36#define SUNXI_R_CPUCFG_BASE 0x07000400
37#define SUNXI_R_PRCM_BASE 0x07010000
38//#define SUNXI_R_WDOG_BASE 0x07020400
39#define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE
40#define SUNXI_R_PIO_BASE 0x07022000
41#define SUNXI_R_UART_BASE 0x07080000
42#define SUNXI_R_I2C_BASE 0x07081400
43#define SUNXI_R_RSB_BASE 0x07083000
44#define SUNXI_CPUCFG_BASE 0x09010000
45
46#endif /* SUNXI_MMAP_H */