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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
johpow01fa59c6f2020-10-02 13:41:11 -050025- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
26 zero at all but the highest implemented exception level. Reads from the
27 memory mapped view are unaffected by this control.
28
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010029- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
31 ``aarch64``.
32
Alexei Fedorov132e6652020-12-07 16:38:53 +000033- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
34 one or more feature modifiers. This option has the form ``[no]feature+...``
35 and defaults to ``none``. It translates into compiler option
36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
37 list of supported feature modifiers.
38
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010039- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
42 :ref:`Firmware Design`.
43
44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
47
48- ``BL2``: This is an optional build option which specifies the path to BL2
49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
50 built.
51
52- ``BL2U``: This is an optional build option which specifies the path to
53 BL2U image. In this case, the BL2U in TF-A will not be built.
54
55- ``BL2_AT_EL3``: This is an optional build option that enables the use of
56 BL2 at EL3 execution level.
57
Balint Dobszay719ba9c2021-03-26 16:23:18 +010058- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the
59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
60
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010061- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
62 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
63 the RW sections in RAM, while leaving the RO sections in place. This option
64 enable this use-case. For now, this option is only supported when BL2_AT_EL3
65 is set to '1'.
66
67- ``BL31``: This is an optional build option which specifies the path to
68 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
69 be built.
70
71- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
72 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
73 this file name will be used to save the key.
74
75- ``BL32``: This is an optional build option which specifies the path to
76 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
77 be built.
78
79- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
80 Trusted OS Extra1 image for the ``fip`` target.
81
82- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
83 Trusted OS Extra2 image for the ``fip`` target.
84
85- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
86 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
87 this file name will be used to save the key.
88
89- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
90 ``fip`` target in case TF-A BL2 is used.
91
92- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
93 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
94 this file name will be used to save the key.
95
96- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
97 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
98 If enabled, it is needed to use a compiler that supports the option
99 ``-mbranch-protection``. Selects the branch protection features to use:
100- 0: Default value turns off all types of branch protection
101- 1: Enables all types of branch protection features
102- 2: Return address signing to its standard level
103- 3: Extend the signing to include leaf functions
Alexei Fedorove039e482020-06-19 14:33:49 +0100104- 4: Turn on branch target identification mechanism
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100105
106 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
107 and resulting PAuth/BTI features.
108
109 +-------+--------------+-------+-----+
110 | Value | GCC option | PAuth | BTI |
111 +=======+==============+=======+=====+
112 | 0 | none | N | N |
113 +-------+--------------+-------+-----+
114 | 1 | standard | Y | Y |
115 +-------+--------------+-------+-----+
116 | 2 | pac-ret | Y | N |
117 +-------+--------------+-------+-----+
118 | 3 | pac-ret+leaf | Y | N |
119 +-------+--------------+-------+-----+
Alexei Fedorove039e482020-06-19 14:33:49 +0100120 | 4 | bti | N | Y |
121 +-------+--------------+-------+-----+
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100122
Manish Pandey34a305e2021-10-21 21:53:49 +0100123 This option defaults to 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100124 Note that Pointer Authentication is enabled for Non-secure world
125 irrespective of the value of this option if the CPU supports it.
126
127- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
128 compilation of each build. It must be set to a C string (including quotes
129 where applicable). Defaults to a string that contains the time and date of
130 the compilation.
131
132- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
133 build to be uniquely identified. Defaults to the current git commit id.
134
Grant Likely388248a2020-07-30 08:50:10 +0100135- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build``
136
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100137- ``CFLAGS``: Extra user options appended on the compiler's command line in
138 addition to the options set by the build system.
139
140- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
141 release several CPUs out of reset. It can take either 0 (several CPUs may be
142 brought up) or 1 (only one CPU will ever be brought up during cold reset).
143 Default is 0. If the platform always brings up a single CPU, there is no
144 need to distinguish between primary and secondary CPUs and the boot path can
145 be optimised. The ``plat_is_my_cpu_primary()`` and
146 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
147 to be implemented in this case.
148
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100149- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
150 Defaults to ``tbbr``.
151
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100152- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
153 register state when an unexpected exception occurs during execution of
154 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
155 this is only enabled for a debug build of the firmware.
156
157- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
158 certificate generation tool to create new keys in case no valid keys are
159 present or specified. Allowed options are '0' or '1'. Default is '1'.
160
161- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
162 the AArch32 system registers to be included when saving and restoring the
163 CPU context. The option must be set to 0 for AArch64-only platforms (that
164 is on hardware that does not implement AArch32, or at least not at EL1 and
165 higher ELs). Default value is 1.
166
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100167- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore
168 operations when entering/exiting an EL2 execution context. This is of primary
169 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled).
170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and
171 ``SPMD_SPM_AT_SEL2`` is set.
172
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
174 registers to be included when saving and restoring the CPU context. Default
175 is 0.
176
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension
178 registers in cpu context. This must be enabled, if the platform wants to use
179 this feature in the Secure world and MTE is enabled at ELX. This flag can
180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
181 Default value is 0.
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100182
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV
184 registers to be saved/restored when entering/exiting an EL2 execution
185 context. This flag can take values 0 to 2, to align with the
186 ``FEATURE_DETECTION`` mechanism. Default value is 0.
187
188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer
189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
190 to be included when saving and restoring the CPU context as part of world
191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION``
192 mechanism. Default value is 0.
193
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100194 Note that Pointer Authentication is enabled for Non-secure world irrespective
195 of the value of this flag if the CPU supports it.
196
197- ``DEBUG``: Chooses between a debug and release build. It can take either 0
198 (release) or 1 (debug) as values. 0 is the default.
199
Sumit Garg392e4df2019-11-15 10:43:00 +0530200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the
201 authenticated decryption algorithm to be used to decrypt firmware/s during
202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of
203 this flag is ``none`` to disable firmware decryption which is an optional
Manish Pandey34a305e2021-10-21 21:53:49 +0100204 feature as per TBBR.
Sumit Garg392e4df2019-11-15 10:43:00 +0530205
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
207 of the binary image. If set to 1, then only the ELF image is built.
208 0 is the default.
209
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
213 check the latest Arm ARM.
214
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
216 Board Boot authentication at runtime. This option is meant to be enabled only
217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
218 flag has to be enabled. 0 is the default.
219
220- ``E``: Boolean option to make warnings into errors. Default is 1.
221
222- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
223 the normal boot flow. It must specify the entry point address of the EL3
224 payload. Please refer to the "Booting an EL3 payload" section for more
225 details.
226
227- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
228 This is an optional architectural feature available on v8.4 onwards. Some
229 v8.2 implementations also implement an AMU and this option can be used to
230 enable this feature on those systems as well. Default is 0.
231
Chris Kay925fda42021-05-25 10:42:56 +0100232- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
233 (also known as group 1 counters). These are implementation-defined counters,
234 and as such require additional platform configuration. Default is 0.
235
Chris Kayf11909f2021-08-19 11:21:52 +0100236- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which
237 allows platforms with auxiliary counters to describe them via the
238 ``HW_CONFIG`` device tree blob. Default is 0.
239
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100240- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
241 are compiled out. For debug builds, this option defaults to 1, and calls to
242 ``assert()`` are left in place. For release builds, this option defaults to 0
243 and calls to ``assert()`` function are compiled out. This option can be set
244 independently of ``DEBUG``. It can also be used to hide any auxiliary code
245 that is only required for the assertion and does not fit in the assertion
246 itself.
247
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000248- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100249 dumps or not. It is supported in both AArch64 and AArch32. However, in
250 AArch32 the format of the frame records are not defined in the AAPCS and they
251 are defined by the implementation. This implementation of backtrace only
252 supports the format used by GCC when T32 interworking is disabled. For this
253 reason enabling this option in AArch32 will force the compiler to only
254 generate A32 code. This option is enabled by default only in AArch64 debug
255 builds, but this behaviour can be overridden in each platform's Makefile or
256 in the build command line.
257
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000258- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000259 (Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000260 to EL3 context save/restore operations. This flag can take the values 0 to 2,
261 to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature
262 available on v8.4 and onwards and must be set to either 1 or 2 alongside
263 ``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register.
264 Default value is ``0``.
265
266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6
268 onwards. This flag can take the values 0 to 2, to align with the
269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
270
271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2``
272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an
274 optional feature available on Arm v8.0 onwards. This flag can take values
275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
276 Default value is ``0``.
277
278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
281 and upwards. This flag can take the values 0 to 2, to align with the
282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000283
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
286 Physical Offset register) during EL2 to EL3 context save/restore operations.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000287 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
289 mechanism. Default value is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000290
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000293 Read Trap Register) during EL2 to EL3 context save/restore operations.
294 Its a mandatory architectural feature and is enabled from v8.6 and upwards.
295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
296 mechanism. Default value is ``0``.
297
298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
301 mandatory architectural feature and is enabled from v8.7 and upwards. This
302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
303 mechanism. Default value is ``0``.
304
305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged
306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a
307 permission fault for any privileged data access from EL1/EL2 to virtual
308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a
309 mandatory architectural feature and is enabled from v8.1 and upwards. This
310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
311 mechanism. Default value is ``0``.
312
313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400316 mechanism. Default value is ``0``.
317
318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP``
319 extension. This feature is only supported in AArch64 state. This flag can
320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from
322 Armv8.5 onwards.
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000323
324- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation
325 Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an
326 optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory
327 for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with
328 ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if
329 needed could be overidden from platforms explicitly. Default value is ``0``.
330
331- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2)
332 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4.
333 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
334 mechanism. Default is ``0``.
Jayanth Dodderi Chidanand76ff3632021-12-05 19:21:14 +0000335
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100336- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed
337 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature
338 available on Arm v8.6. This flag can take values 0 to 2, to align with the
339 ``FEATURE_DETECTION`` mechanism. Default is ``0``.
340
341 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets
342 delayed by the amount of value in ``TWED_DELAY``.
343
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000344- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization
345 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
346 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory
347 architectural feature and is enabled from v8.1 and upwards. It can take
348 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism.
349 Default value is ``0``.
johpow01f91e59f2021-08-04 19:38:18 -0500350
Sandrine Bailleux11427302019-12-17 09:38:08 +0100351- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600352 support in GCC for TF-A. This option is currently only supported for
353 AArch64. Default is 0.
354
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000355- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100356 feature. MPAM is an optional Armv8.4 extension that enables various memory
357 system components and resources to define partitions; software running at
358 various ELs can assign themselves to desired partition to control their
359 performance aspects.
360
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000361 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION``
362 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to
363 access their own MPAM registers without trapping into EL3. This option
364 doesn't make use of partitioning in EL3, however. Platform initialisation
365 code should configure and use partitions in EL3 as required. This option
366 defaults to ``0``.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100367
Chris Kay03be39d2021-05-05 13:38:30 +0100368- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
369 Mitigation Mechanism supported by certain Arm cores, which allows the SoC
370 firmware to detect and limit high activity events to assist in SoC processor
371 power domain dynamic power budgeting and limit the triggering of whole-rail
372 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.
373
374- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which
375 allows platforms with cores supporting MPMM to describe them via the
376 ``HW_CONFIG`` device tree blob. Default is 0.
377
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100378- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
379 support within generic code in TF-A. This option is currently only supported
Yann Gautier514e59c2020-10-05 11:02:54 +0200380 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
381 (SP_min) for AARCH32. Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100382
383- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
384 Measurement Framework(PMF). Default is 0.
385
386- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
387 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
388 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
389 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
390 software.
391
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000392- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm
393 Management Extension. This flag can take the values 0 to 2, to align with
394 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently
395 an experimental feature.
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500396
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100397- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
398 instrumentation which injects timestamp collection points into TF-A to
399 allow runtime performance to be measured. Currently, only PSCI is
400 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
401 as well. Default is 0.
402
johpow019baade32021-07-08 14:14:00 -0500403- ``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension
404 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share
405 registers so are enabled together. Using this option without
406 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
407 world to trap to EL3. SME is an optional architectural feature for AArch64
408 and TF-A support is experimental. At this time, this build option cannot be
Manish Pandey247e5c32021-11-15 15:29:08 +0000409 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
410 build with these options will fail. Default is 0.
johpow019baade32021-07-08 14:14:00 -0500411
412- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
413 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
414 must also be set to use this. If enabling this, the secure world MUST
415 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
416 no data is leaked to non-secure world. This is experimental. Default is 0.
417
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100418- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
419 extensions. This is an optional architectural feature for AArch64.
420 The default is 1 but is automatically disabled when the target architecture
421 is AArch32.
422
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100423- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
424 (SVE) for the Non-secure world only. SVE is an optional architectural feature
425 for AArch64. Note that when SVE is enabled for the Non-secure world, access
Max Shvetsovc4502772021-03-22 11:59:37 +0000426 to SIMD and floating-point functionality from the Secure world is disabled by
427 default and controlled with ENABLE_SVE_FOR_SWD.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100428 This is to avoid corruption of the Non-secure world data in the Z-registers
429 which are aliased by the SIMD and FP registers. The build option is not
430 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
431 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
johpow019baade32021-07-08 14:14:00 -0500432 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1
Manish Pandey247e5c32021-11-15 15:29:08 +0000433 since SME encompasses SVE. At this time, this build option cannot be used on
434 systems that have SPM_MM enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100435
Max Shvetsovc4502772021-03-22 11:59:37 +0000436- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
437 SVE is an optional architectural feature for AArch64. Note that this option
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000438 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it
439 is automatically disabled when the target architecture is AArch32.
Max Shvetsovc4502772021-03-22 11:59:37 +0000440
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100441- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
442 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
443 default value is set to "none". "strong" is the recommended stack protection
444 level if this feature is desired. "none" disables the stack protection. For
445 all values other than "none", the ``plat_get_stack_protector_canary()``
446 platform hook needs to be implemented. The value is passed as the last
447 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
448
Sumit Gargc0c369c2019-11-15 18:47:53 +0530449- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
Manish Pandey34a305e2021-10-21 21:53:49 +0100450 flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530451
452- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload.
Manish Pandey34a305e2021-10-21 21:53:49 +0100453 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530454
455- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could
456 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends
Manish Pandey34a305e2021-10-21 21:53:49 +0100457 on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530458
459- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector
460 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT``
Manish Pandey34a305e2021-10-21 21:53:49 +0100461 build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530462
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100463- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
464 deprecated platform APIs, helper functions or drivers within Trusted
465 Firmware as error. It can take the value 1 (flag the use of deprecated
466 APIs as error) or 0. The default is 0.
467
468- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
469 targeted at EL3. When set ``0`` (default), no exceptions are expected or
Raghu Krishnamurthy669bf402022-07-25 14:44:33 -0700470 handled at EL3, and a panic will result. The exception to this rule is when
471 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions
472 occuring during normal world execution, are trapped to EL3. Any exception
473 trapped during secure world execution are trapped to the SPMC. This is
474 supported only for AArch64 builds.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100475
Javier Almansa Sobrino0d1f6b12020-09-18 16:47:07 +0100476- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when
477 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``.
478 Default value is 40 (LOG_LEVEL_INFO).
479
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100480- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
481 injection from lower ELs, and this build option enables lower ELs to use
482 Error Records accessed via System Registers to inject faults. This is
483 applicable only to AArch64 builds.
484
485 This feature is intended for testing purposes only, and is advisable to keep
486 disabled for production images.
487
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000488- ``FEATURE_DETECTION``: Boolean option to enable the architectural features
489 detection mechanism. It detects whether the Architectural features enabled
490 through feature specific build flags are supported by the PE or not by
491 validating them either at boot phase or at runtime based on the value
492 possessed by the feature flag (0 to 2) and report error messages at an early
493 stage.
494
495 This prevents and benefits us from EL3 runtime exceptions during context save
496 and restore routines guarded by these build flags. Henceforth validating them
497 before their usage provides more control on the actions taken under them.
498
499 The mechanism permits the build flags to take values 0, 1 or 2 and
500 evaluates them accordingly.
501
502 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example:
503
504 ::
505
506 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time.
507 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime.
508 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime.
509
510 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to
511 0, feature is disabled statically during compilation. If it is defined as 1,
512 feature is validated, wherein FEAT_HCX is detected at boot time. In case not
513 implemented by the PE, a hard panic is generated. Finally, if the flag is set
514 to 2, feature is validated at runtime.
515
516 Note that the entire implementation is divided into two phases, wherein as
517 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not
518 supported and is planned to be handled explicilty in phase-2 implementation.
519
520 FEATURE_DETECTION macro is disabled by default, and is currently an
521 experimental procedure. Platforms can explicitly make use of this by
522 mechanism, by enabling it to validate whether they have set their build flags
523 properly at an early phase.
524
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100525- ``FIP_NAME``: This is an optional build option which specifies the FIP
526 filename for the ``fip`` target. Default is ``fip.bin``.
527
528- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
529 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
530
Sumit Gargc0c369c2019-11-15 18:47:53 +0530531- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:
532
533 ::
534
535 0: Encryption is done with Secret Symmetric Key (SSK) which is common
536 for a class of devices.
537 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is
538 unique per device.
539
Manish Pandey34a305e2021-10-21 21:53:49 +0100540 This flag depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530541
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100542- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
543 tool to create certificates as per the Chain of Trust described in
544 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
545 include the certificates in the FIP and FWU_FIP. Default value is '0'.
546
547 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
548 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
549 the corresponding certificates, and to include those certificates in the
550 FIP and FWU_FIP.
551
552 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
553 images will not include support for Trusted Board Boot. The FIP will still
554 include the corresponding certificates. This FIP can be used to verify the
555 Chain of Trust on the host machine through other mechanisms.
556
557 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
558 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
559 will not include the corresponding certificates, causing a boot failure.
560
561- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
562 inherent support for specific EL3 type interrupts. Setting this build option
563 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500564 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and
565 :ref:`Interrupt Management Framework<Interrupt Management Framework>`.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100566 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
567 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
568 the Secure Payload interrupts needs to be synchronously handed over to Secure
569 EL1 for handling. The default value of this option is ``0``, which means the
570 Group 0 interrupts are assumed to be handled by Secure EL1.
571
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100572- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
573 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
574 ``0`` (default), these exceptions will be trapped in the current exception
575 level (or in EL1 if the current exception level is EL0).
576
577- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
578 software operations are required for CPUs to enter and exit coherency.
579 However, newer systems exist where CPUs' entry to and exit from coherency
580 is managed in hardware. Such systems require software to only initiate these
581 operations, and the rest is managed in hardware, minimizing active software
582 management. In such systems, this boolean option enables TF-A to carry out
583 build and run-time optimizations during boot and power management operations.
584 This option defaults to 0 and if it is enabled, then it implies
585 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
586
587 If this flag is disabled while the platform which TF-A is compiled for
588 includes cores that manage coherency in hardware, then a compilation error is
589 generated. This is based on the fact that a system cannot have, at the same
590 time, cores that manage coherency in hardware and cores that don't. In other
591 words, a platform cannot have, at the same time, cores that require
592 ``HW_ASSISTED_COHERENCY=1`` and cores that require
593 ``HW_ASSISTED_COHERENCY=0``.
594
595 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
596 translation library (xlat tables v2) must be used; version 1 of translation
597 library is not supported.
598
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000599- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000600 bottom, higher addresses at the top. This build flag can be set to '1' to
Louis Mayencourtc1c2bf72020-02-13 08:21:34 +0000601 invert this behavior. Lower addresses will be printed at the top and higher
602 addresses at the bottom.
603
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100604- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
605 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
606 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
607 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
608 images.
609
610- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
611 used for generating the PKCS keys and subsequent signing of the certificate.
612 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
613 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
614 compliant and is retained only for compatibility. The default value of this
615 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
616
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300617- ``KEY_SIZE``: This build flag enables the user to select the key size for
618 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
619 depend on the chosen algorithm and the cryptographic module.
620
621 +-----------+------------------------------------+
622 | KEY_ALG | Possible key sizes |
623 +===========+====================================+
624 | rsa | 1024 , 2048 (default), 3072, 4096* |
625 +-----------+------------------------------------+
626 | ecdsa | unavailable |
627 +-----------+------------------------------------+
628
629 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
630 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
631
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100632- ``HASH_ALG``: This build flag enables the user to select the secure hash
633 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
634 The default value of this flag is ``sha256``.
635
636- ``LDFLAGS``: Extra user options appended to the linkers' command line in
637 addition to the one set by the build system.
638
639- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
640 output compiled into the build. This should be one of the following:
641
642 ::
643
644 0 (LOG_LEVEL_NONE)
645 10 (LOG_LEVEL_ERROR)
646 20 (LOG_LEVEL_NOTICE)
647 30 (LOG_LEVEL_WARNING)
648 40 (LOG_LEVEL_INFO)
649 50 (LOG_LEVEL_VERBOSE)
650
651 All log output up to and including the selected log level is compiled into
652 the build. The default value is 40 in debug builds and 20 in release builds.
653
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000654- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
Manish V Badarkhe92de80a2021-12-16 10:41:47 +0000655 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to
656 provide trust that the code taking the measurements and recording them has
657 not been tampered with.
Sandrine Bailleux533d8b32021-06-10 11:18:04 +0200658
Manish Pandey34a305e2021-10-21 21:53:49 +0100659 This option defaults to 0.
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000660
Manish V Badarkhe8564f772022-02-14 18:31:16 +0000661- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
662 for Measurement (DRTM). This feature has trust dependency on BL31 for taking
663 the measurements and recording them as per `PSA DRTM specification`_. For
664 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can
665 be used and for the platforms which use ``RESET_TO_BL31`` platform owners
666 should have mechanism to authenticate BL31.
667
668 This option defaults to 0.
669
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100670- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
671 specifies the file that contains the Non-Trusted World private key in PEM
672 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
673
674- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
675 optional. It is only needed if the platform makefile specifies that it
676 is required in order to build the ``fwu_fip`` target.
677
678- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
679 contents upon world switch. It can take either 0 (don't save and restore) or
680 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
681 wants the timer registers to be saved and restored.
682
683- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
684 for the BL image. It can be either 0 (include) or 1 (remove). The default
685 value is 0.
686
687- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
688 the underlying hardware is not a full PL011 UART but a minimally compliant
689 generic UART, which is a subset of the PL011. The driver will not access
690 any register that is not part of the SBSA generic UART specification.
691 Default value is 0 (a full PL011 compliant UART is present).
692
693- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
694 must be subdirectory of any depth under ``plat/``, and must contain a
695 platform makefile named ``platform.mk``. For example, to build TF-A for the
696 Arm Juno board, select PLAT=juno.
697
698- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
699 instead of the normal boot flow. When defined, it must specify the entry
700 point address for the preloaded BL33 image. This option is incompatible with
701 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
702 over ``PRELOADED_BL33_BASE``.
703
704- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
705 vector address can be programmed or is fixed on the platform. It can take
706 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
707 programmable reset address, it is expected that a CPU will start executing
708 code directly at the right address, both on a cold and warm reset. In this
709 case, there is no need to identify the entrypoint on boot and the boot path
710 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
711 does not need to be implemented in this case.
712
713- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
714 possible for the PSCI power-state parameter: original and extended State-ID
715 formats. This flag if set to 1, configures the generic PSCI layer to use the
716 extended format. The default value of this flag is 0, which means by default
717 the original power-state format is used by the PSCI implementation. This flag
718 should be specified by the platform makefile and it governs the return value
719 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
720 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
721 set to 1 as well.
722
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000723- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100724 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000725 or later CPUs. This flag can take the values 0 to 2, to align with the
726 ``FEATURE_DETECTION`` mechanism.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100727
728 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
729 set to ``1``.
730
731 This option is disabled by default.
732
733- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
734 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
735 entrypoint) or 1 (CPU reset to BL31 entrypoint).
736 The default value is 0.
737
Jorge Ramirez-Ortiz598db322022-04-15 11:51:03 +0200738- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting
739 this additional option guarantees that the input registers are not cleared
740 therefore allowing parameters to be passed to the BL31 entrypoint.
741 The default value is 0.
742
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100743- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
744 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
745 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
746 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
747
748- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000749 file that contains the ROT private key in PEM format and enforces public key
750 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100751 file name will be used to save the key.
752
753- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
754 certificate generation tool to save the keys used to establish the Chain of
755 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
756
757- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
758 If a SCP_BL2 image is present then this option must be passed for the ``fip``
759 target.
760
761- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
762 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
763 this file name will be used to save the key.
764
765- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
766 optional. It is only needed if the platform makefile specifies that it
767 is required in order to build the ``fwu_fip`` target.
768
769- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
770 Delegated Exception Interface to BL31 image. This defaults to ``0``.
771
772 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
773 set to ``1``.
774
775- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
776 isolated on separate memory pages. This is a trade-off between security and
777 memory usage. See "Isolating code and read-only data on separate memory
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100778 pages" section in :ref:`Firmware Design`. This flag is disabled by default
779 and affects all BL images.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100780
Samuel Holland31a14e12018-10-17 21:40:18 -0500781- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
782 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
783 allocated in RAM discontiguous from the loaded firmware image. When set, the
David Horstmannb2cc35f2021-01-21 12:29:59 +0000784 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
Samuel Holland31a14e12018-10-17 21:40:18 -0500785 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
786 sections are placed in RAM immediately following the loaded firmware image.
787
Jiafei Pan0824b452022-02-24 10:47:33 +0800788- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the
789 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM
790 discontiguous from loaded firmware images. When set, the platform need to
791 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This
792 flag is disabled by default and NOLOAD sections are placed in RAM immediately
793 following the loaded firmware image.
794
Jeremy Linton684a0792021-01-26 22:42:03 -0600795- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
796 access requests via a standard SMCCC defined in `DEN0115`_. When combined with
797 UEFI+ACPI this can provide a certain amount of OS forward compatibility
798 with newer platforms that aren't ECAM compliant.
799
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100800- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
801 This build option is only valid if ``ARCH=aarch64``. The value should be
802 the path to the directory containing the SPD source, relative to
803 ``services/spd/``; the directory is expected to contain a makefile called
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100804 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
805 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
806 cannot be enabled when the ``SPM_MM`` option is enabled.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100807
808- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
809 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
810 execution in BL1 just before handing over to BL31. At this point, all
811 firmware images have been loaded in memory, and the MMU and caches are
812 turned off. Refer to the "Debugging options" section for more details.
813
Marc Bonniciabaac162021-12-01 18:00:40 +0000814- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM
815 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
816 component runs at the EL3 exception level. The default value is ``0`` (
817 disabled). This configuration supports pre-Armv8.4 platforms (aka not
818 implementing the ``FEAT_SEL2`` extension). This is an experimental feature.
819
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +0000820- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100821 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
Marc Bonniciabaac162021-12-01 18:00:40 +0000822 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2``
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100823 extension. This is the default when enabling the SPM Dispatcher. When
824 disabled (0) it indicates the SPMC component runs at the S-EL1 execution
Marc Bonniciabaac162021-12-01 18:00:40 +0000825 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations
826 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2``
827 extension).
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100828
Paul Beesleyfe975b42019-09-16 11:29:03 +0000829- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100830 Partition Manager (SPM) implementation. The default value is ``0``
831 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
832 enabled (``SPD=spmd``).
Paul Beesleyfe975b42019-09-16 11:29:03 +0000833
Manish Pandey3f90ad72020-01-14 11:52:05 +0000834- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
Olivier Deprez7efa3f12020-03-26 16:09:21 +0100835 description of secure partitions. The build system will parse this file and
836 package all secure partition blobs into the FIP. This file is not
837 necessarily part of TF-A tree. Only available when ``SPD=spmd``.
Manish Pandey3f90ad72020-01-14 11:52:05 +0000838
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100839- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
840 secure interrupts (caught through the FIQ line). Platforms can enable
841 this directive if they need to handle such interruption. When enabled,
842 the FIQ are handled in monitor mode and non secure world is not allowed
843 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
844 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
845
Mark Brown64869972022-04-20 18:14:32 +0100846- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3.
847 Platforms can configure this if they need to lower the hardware
848 limit, for example due to asymmetric configuration or limitations of
849 software run at lower ELs. The default is the architectural maximum
850 of 2048 which should be suitable for most configurations, the
851 hardware will limit the effective VL to the maximum physically supported
852 VL.
853
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100854- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
855 Boot feature. When set to '1', BL1 and BL2 images include support to load
856 and verify the certificates and images in a FIP, and BL1 includes support
857 for the Firmware Update. The default value is '0'. Generation and inclusion
858 of certificates in the FIP and FWU_FIP depends upon the value of the
859 ``GENERATE_COT`` option.
860
861 .. warning::
862 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
863 already exist in disk, they will be overwritten without further notice.
864
865- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
866 specifies the file that contains the Trusted World private key in PEM
867 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
868
869- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
870 synchronous, (see "Initializing a BL32 Image" section in
871 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
872 synchronous method) or 1 (BL32 is initialized using asynchronous method).
873 Default is 0.
874
875- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
876 routing model which routes non-secure interrupts asynchronously from TSP
877 to EL3 causing immediate preemption of TSP. The EL3 is responsible
878 for saving and restoring the TSP context in this routing model. The
879 default routing model (when the value is 0) is to route non-secure
880 interrupts to TSP allowing it to save its context and hand over
881 synchronously to EL3 via an SMC.
882
883 .. note::
884 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
885 must also be set to ``1``.
886
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100887- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
888 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set
889 this delay. It can take values in the range (0-15). Default value is ``0``
890 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed.
891 Platforms need to explicitly update this value based on their requirements.
892
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100893- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
894 linker. When the ``LINKER`` build variable points to the armlink linker,
895 this flag is enabled automatically. To enable support for armlink, platforms
896 will have to provide a scatter file for the BL image. Currently, Tegra
897 platforms use the armlink support to compile BL3-1 images.
898
899- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
900 memory region in the BL memory map or not (see "Use of Coherent memory in
901 TF-A" section in :ref:`Firmware Design`). It can take the value 1
902 (Coherent memory region is included) or 0 (Coherent memory region is
903 excluded). Default is 1.
904
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100905- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
906 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
907 Default is 0.
908
Louis Mayencourt6b232d92020-02-28 16:57:30 +0000909- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
910 firmware configuration framework. This will move the io_policies into a
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100911 configuration device tree, instead of static structure in the code base.
912
Manish V Badarkhead339892020-06-29 10:32:53 +0100913- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors
914 at runtime using fconf. If this flag is enabled, COT descriptors are
915 statically captured in tb_fw_config file in the form of device tree nodes
916 and properties. Currently, COT descriptors used by BL2 are moved to the
917 device tree and COT descriptors used by BL1 are retained in the code
Manish Pandey34a305e2021-10-21 21:53:49 +0100918 base statically.
Manish V Badarkhead339892020-06-29 10:32:53 +0100919
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100920- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in
921 runtime using firmware configuration framework. The platform specific SDEI
922 shared and private events configuration is retrieved from device tree rather
Manish Pandey34a305e2021-10-21 21:53:49 +0100923 than static C structures at compile time. This is only supported if
924 SDEI_SUPPORT build flag is enabled.
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100925
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500926- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
927 and Group1 secure interrupts using the firmware configuration framework. The
928 platform specific secure interrupt property descriptor is retrieved from
929 device tree in runtime rather than depending on static C structure at compile
Manish Pandey34a305e2021-10-21 21:53:49 +0100930 time.
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500931
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100932- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
933 This feature creates a library of functions to be placed in ROM and thus
934 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
935 is 0.
936
937- ``V``: Verbose build. If assigned anything other than 0, the build commands
938 are printed. Default is 0.
939
940- ``VERSION_STRING``: String used in the log output for each TF-A image.
941 Defaults to a string formed by concatenating the version number, build type
942 and build string.
943
944- ``W``: Warning level. Some compiler warning options of interest have been
945 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
946 each level enabling more warning options. Default is 0.
947
948- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
949 the CPU after warm boot. This is applicable for platforms which do not
950 require interconnect programming to enable cache coherency (eg: single
951 cluster platforms). If this option is enabled, then warm boot path
952 enables D-caches immediately after enabling MMU. This option defaults to 0.
953
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000954- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
955 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
956 default value of this flag is ``no``. Note this option must be enabled only
957 for ARM architecture greater than Armv8.5-A.
958
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100959- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
960 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
961 The default value of this flag is ``0``.
962
963 ``AT`` speculative errata workaround disables stage1 page table walk for
964 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
965 produces either the correct result or failure without TLB allocation.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100966
967 This boolean option enables errata for all below CPUs.
968
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100969 +---------+--------------+-------------------------+
970 | Errata | CPU | Workaround Define |
971 +=========+==============+=========================+
972 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
973 +---------+--------------+-------------------------+
974 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
975 +---------+--------------+-------------------------+
976 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
977 +---------+--------------+-------------------------+
978 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
979 +---------+--------------+-------------------------+
980 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
981 +---------+--------------+-------------------------+
982
983 .. note::
984 This option is enabled by build only if platform sets any of above defines
985 mentioned in ’Workaround Define' column in the table.
986 If this option is enabled for the EL3 software then EL2 software also must
987 implement this workaround due to the behaviour of the errata mentioned
988 in new SDEN document which will get published soon.
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100989
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100990- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
Varun Wadekar92234852020-06-12 10:11:28 -0700991 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
992 This flag is disabled by default.
993
Juan Pablo Conde52865522022-06-28 16:56:32 -0400994- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the
995 host machine where a custom installation of OpenSSL is located, which is used
996 to build the certificate generation, firmware encryption and FIP tools. If
997 this option is not set, the default OS installation will be used.
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100998
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500999- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for
1000 functions that wait for an arbitrary time length (udelay and mdelay). The
1001 default value is 0.
1002
Jayanth Dodderi Chidanand69316752022-05-09 12:33:03 +01001003- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record
1004 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1005 optional architectural feature for AArch64. This flag can take the values
1006 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0
1007 and it is automatically disabled when the target architecture is AArch32.
johpow0181865962022-01-28 17:06:20 -06001008
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001009- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001010 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1011 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural
Jayanth Dodderi Chidananda793ccc2022-05-19 14:08:28 +01001012 feature for AArch64. This flag can take the values 0 to 2, to align with the
1013 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically
1014 disabled when the target architecture is AArch32.
Manish V Badarkhe20df29c2021-07-02 09:10:56 +01001015
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001016- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system
1017 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1018 but unused). This feature is available if trace unit such as ETMv4.x, and
1019 ETE(extending ETM feature) is implemented. This flag is disabled by default.
1020
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001021- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001022 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused),
Jayanth Dodderi Chidanand38b461a2022-02-28 23:41:41 +00001023 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align
1024 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default.
Manish V Badarkhe51a97112021-07-08 09:33:18 +01001025
Tamas Banc9ccc272022-01-18 16:20:47 +01001026- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA
1027 APIs on platforms that doesn't support RSS (providing Arm CCA HES
1028 functionalities). When enabled (``1``), a mocked version of the APIs are used.
1029 The default value is 0.
1030
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001031GICv3 driver options
1032--------------------
1033
1034GICv3 driver files are included using directive:
1035
1036``include drivers/arm/gic/v3/gicv3.mk``
1037
1038The driver can be configured with the following options set in the platform
1039makefile:
1040
Andre Przywarae1cc1302020-03-25 15:50:38 +00001041- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3.
1042 Enabling this option will add runtime detection support for the
1043 GIC-600, so is safe to select even for a GIC500 implementation.
1044 This option defaults to 0.
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001045
Varun Wadekareea6dc12021-05-04 16:14:09 -07001046- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit
1047 for GIC-600 AE. Enabling this option will introduce support to initialize
1048 the FMU. Platforms should call the init function during boot to enable the
1049 FMU and its safety mechanisms. This option defaults to 0.
1050
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +00001051- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
1052 functionality. This option defaults to 0
1053
1054- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
1055 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
1056 functions. This is required for FVP platform which need to simulate GIC save
1057 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
1058
Alexei Fedorov19705932020-04-06 19:00:35 +01001059- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver.
1060 This option defaults to 0.
1061
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001062- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended
1063 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.
1064
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001065Debugging options
1066-----------------
1067
1068To compile a debug version and make the build more verbose use
1069
1070.. code:: shell
1071
1072 make PLAT=<platform> DEBUG=1 V=1 all
1073
Daniel Boulbydf83a832022-05-03 16:46:16 +01001074AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools
1075(for example Arm-DS) might not support this and may need an older version of
1076DWARF symbols to be emitted by GCC. This can be achieved by using the
1077``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting
1078the version to 4 is recommended for Arm-DS.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001079
1080When debugging logic problems it might also be useful to disable all compiler
1081optimizations by using ``-O0``.
1082
1083.. warning::
1084 Using ``-O0`` could cause output images to be larger and base addresses
1085 might need to be recalculated (see the **Memory layout on Arm development
1086 platforms** section in the :ref:`Firmware Design`).
1087
1088Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1089``LDFLAGS``:
1090
1091.. code:: shell
1092
1093 CFLAGS='-O0 -gdwarf-2' \
1094 make PLAT=<platform> DEBUG=1 V=1 all
1095
1096Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1097ignored as the linker is called directly.
1098
1099It is also possible to introduce an infinite loop to help in debugging the
1100post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1101``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
1102section. In this case, the developer may take control of the target using a
Daniel Boulbydf83a832022-05-03 16:46:16 +01001103debugger when indicated by the console output. When using Arm-DS, the following
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001104commands can be used:
1105
1106::
1107
1108 # Stop target execution
1109 interrupt
1110
1111 #
1112 # Prepare your debugging environment, e.g. set breakpoints
1113 #
1114
1115 # Jump over the debug loop
1116 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1117
1118 # Resume execution
1119 continue
1120
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001121Firmware update options
1122-----------------------
1123
1124- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
1125 in defining the firmware update metadata structure. This flag is by default
1126 set to '2'.
1127
1128- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
1129 firmware bank. Each firmware bank must have the same number of images as per
1130 the `PSA FW update specification`_.
1131 This flag is used in defining the firmware update metadata structure. This
1132 flag is by default set to '1'.
1133
Manish V Badarkheda87af12021-06-20 21:14:46 +01001134- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
1135 `PSA FW update specification`_. The default value is 0, and this is an
1136 experimental feature.
1137 PSA firmware update implementation has some limitations, such as BL2 is
1138 not part of the protocol-updatable images, if BL2 needs to be updated, then
1139 it should be done through another platform-defined mechanism, and it assumes
1140 that the platform's hardware supports CRC32 instructions.
1141
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001142--------------
1143
Jiafei Pan0824b452022-02-24 10:47:33 +08001144*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
Jeremy Linton684a0792021-01-26 22:42:03 -06001145
1146.. _DEN0115: https://developer.arm.com/docs/den0115/latest
Manish V Badarkhe5c101ae2021-03-16 11:14:19 +00001147.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
Manish V Badarkhe8564f772022-02-14 18:31:16 +00001148.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a