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Andre Przywara6d471e12019-07-09 11:25:57 +01001/*
Jeremy Linton58c99742020-11-18 10:17:15 -06002 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
Andre Przywara6d471e12019-07-09 11:25:57 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef RPI_HW_H
8#define RPI_HW_H
9
10#include <lib/utils_def.h>
11
12/*
13 * Peripherals
14 */
15
Jeremy Linton58c99742020-11-18 10:17:15 -060016#define RPI_IO_BASE ULL(0xFC000000)
17#define RPI_IO_SIZE ULL(0x04000000)
18
19#define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE)
Andre Przywara6d471e12019-07-09 11:25:57 +010020
21/*
22 * ARM <-> VideoCore mailboxes
23 */
24#define RPI3_MBOX_OFFSET ULL(0x0000B880)
Jeremy Linton58c99742020-11-18 10:17:15 -060025#define RPI3_MBOX_BASE (RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010026/* VideoCore -> ARM */
27#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
28#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
29#define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
30#define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
31#define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
32/* ARM -> VideoCore */
33#define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
34#define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
35#define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034)
36#define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038)
37#define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C)
38/* Mailbox status constants */
39#define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */
40#define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */
41
42/*
43 * Power management, reset controller, watchdog.
44 */
45#define RPI3_IO_PM_OFFSET ULL(0x00100000)
Jeremy Linton58c99742020-11-18 10:17:15 -060046#define RPI3_PM_BASE (RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010047/* Registers on top of RPI3_PM_BASE. */
48#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
49#define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
50#define RPI3_PM_WDOG_OFFSET ULL(0x00000024)
51/* Watchdog constants */
52#define RPI3_PM_PASSWORD U(0x5A000000)
53#define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030)
54#define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020)
55/*
56 * The RSTS register is used by the VideoCore firmware when booting the
57 * Raspberry Pi to know which partition to boot from. The partition value is
58 * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware
59 * to indicate halt.
60 */
61#define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555)
62
63/*
Andre Przywara6d471e12019-07-09 11:25:57 +010064 * Hardware random number generator.
65 */
66#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
Jeremy Linton58c99742020-11-18 10:17:15 -060067#define RPI3_RNG_BASE (RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010068#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000)
69#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004)
70#define RPI3_RNG_DATA_OFFSET ULL(0x00000008)
71#define RPI3_RNG_INT_MASK_OFFSET ULL(0x00000010)
72/* Enable/disable RNG */
73#define RPI3_RNG_CTRL_ENABLE U(0x1)
74#define RPI3_RNG_CTRL_DISABLE U(0x0)
75/* Number of currently available words */
76#define RPI3_RNG_STATUS_NUM_WORDS_SHIFT U(24)
77#define RPI3_RNG_STATUS_NUM_WORDS_MASK U(0xFF)
78/* Value to mask interrupts caused by the RNG */
79#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
80
81/*
Andre Przywara9ba6bb02020-03-10 12:34:56 +000082 * Serial ports:
83 * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
84 * There is also a PL011 UART, multiplexed to the same pins.
Andre Przywara6d471e12019-07-09 11:25:57 +010085 */
Andre Przywara57ccecc2020-03-10 12:33:16 +000086#define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
Jeremy Linton58c99742020-11-18 10:17:15 -060087#define RPI4_MINI_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET)
Andre Przywara9ba6bb02020-03-10 12:34:56 +000088#define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
Jeremy Linton58c99742020-11-18 10:17:15 -060089#define RPI4_PL011_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET)
Andre Przywara9ba6bb02020-03-10 12:34:56 +000090#define RPI4_PL011_UART_CLOCK ULL(48000000)
Andre Przywara6d471e12019-07-09 11:25:57 +010091
92/*
93 * GPIO controller
94 */
95#define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
Jeremy Linton58c99742020-11-18 10:17:15 -060096#define RPI3_GPIO_BASE (RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +010097
98/*
99 * SDHost controller
100 */
101#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
Jeremy Linton58c99742020-11-18 10:17:15 -0600102#define RPI3_SDHOST_BASE (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET)
Andre Przywara6d471e12019-07-09 11:25:57 +0100103
104/*
105 * GIC interrupt controller
106 */
107#define RPI_HAVE_GIC
108#define RPI4_GIC_GICD_BASE ULL(0xff841000)
109#define RPI4_GIC_GICC_BASE ULL(0xff842000)
110
111#define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000)
112#define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008)
113
114#endif /* RPI_HW_H */