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git01.mediatek.com / filogic / atf / fc4f80e3b60c578cb9141e148c53380a0e89812a / . / plat / arm / board / rdn1edge / platform.mk
blob: e43654292d6bd71ad54a7b3ad994404dfd611ff2 [file] [log] [blame]
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]1#
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]2# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]7# GIC-600 configuration
8GICV3_IMPL_GIC600_MULTICHIP := 1
9
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]10include plat/arm/css/sgi/sgi-common.mk
11
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]12RDN1EDGE_BASE = plat/arm/board/rdn1edge
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]13
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]14PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]15
John Tsichritzis56369c12019-02-19 13:49:06 +0000[diff] [blame]16SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]17
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]18BL1_SOURCES += ${SGI_CPU_SOURCES} \
19 ${RDN1EDGE_BASE}/rdn1edge_err.c
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]20
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]21BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \
22 ${RDN1EDGE_BASE}/rdn1edge_security.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]23 ${RDN1EDGE_BASE}/rdn1edge_err.c \
Vijayenthiran Subramaniam22141b62018-10-25 22:20:24 +0530[diff] [blame]24 drivers/arm/tzc/tzc_dmc620.c \
25 lib/utils/mem_region.c \
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]26 plat/arm/common/arm_nor_psci_mem_protect.c
27
28BL31_SOURCES += ${SGI_CPU_SOURCES} \
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]29 ${RDN1EDGE_BASE}/rdn1edge_plat.c \
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]30 ${RDN1EDGE_BASE}/rdn1edge_topology.c \
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]31 drivers/cfi/v2m/v2m_flash.c \
32 lib/utils/mem_region.c \
33 plat/arm/common/arm_nor_psci_mem_protect.c
34
Max Shvetsov06dba292019-12-06 11:50:12 +0000[diff] [blame]35ifeq (${TRUSTED_BOARD_BOOT}, 1)
36BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
37BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
38endif
39
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]40# Enable dynamic addition of MMAP regions in BL31
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900[diff] [blame]41BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]42
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]43# Add the FDT_SOURCES and options for Dynamic Config
Louis Mayencourt9fdfae32020-02-12 09:26:09 +0000[diff] [blame]44FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts
45TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]46
47# Add the TB_FW_CONFIG to FIP and specify the same to certtool
48$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
49
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]50FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
Chandni Cherukuri29ea98d2018-11-28 11:26:19 +0530[diff] [blame]51NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]52
Chandni Cherukuri29ea98d2018-11-28 11:26:19 +0530[diff] [blame]53# Add the NT_FW_CONFIG to FIP and specify the same to certtool
54$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]55
Vijayenthiran Subramaniamcfa3aea2020-02-12 13:26:33 +0530[diff] [blame]56$(eval $(call CREATE_SEQ,SEQ,2))
57ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
58 $(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]59 set to ${CSS_SGI_CHIP_COUNT}.")
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]60endif
61
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]62override CTX_INCLUDE_AARCH32_REGS := 0