Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
Derek Basehore | c8e5c78 | 2017-02-24 14:33:03 +0800 | [diff] [blame] | 34 | #include <delay_timer.h> |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 35 | #include <mmio.h> |
| 36 | #include <m0_ctl.h> |
| 37 | #include <plat_private.h> |
| 38 | #include <rk3399_def.h> |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 39 | #include <secure.h> |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 40 | #include <soc.h> |
| 41 | |
| 42 | void m0_init(void) |
| 43 | { |
| 44 | /* secure config for M0 */ |
| 45 | mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 46 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 47 | |
| 48 | /* set the execute address for M0 */ |
| 49 | mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3), |
| 50 | BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff, |
| 51 | 0xffff, 0)); |
| 52 | mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7), |
| 53 | BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, |
| 54 | 0xf, 0)); |
| 55 | |
Lin Huang | 8140b7d | 2016-12-30 13:53:25 +0800 | [diff] [blame] | 56 | /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ |
| 57 | mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 58 | |
| 59 | /* |
| 60 | * To switch the parent to xin24M and div == 1, |
| 61 | * |
| 62 | * We need to close most of the PLLs and clocks except the OSC 24MHz |
| 63 | * durning suspend, and this should be enough to supplies the ddrfreq, |
| 64 | * For the simple handle, we just keep the fixed 24MHz to supply the |
| 65 | * suspend and ddrfreq directly. |
| 66 | */ |
| 67 | mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, |
| 68 | BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 69 | |
| 70 | mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | void m0_start(void) |
| 74 | { |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 75 | /* enable clocks for M0 */ |
| 76 | mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, |
| 77 | BITS_WITH_WMASK(0x0, 0xf, 0)); |
| 78 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 79 | /* clean the PARAM_M0_DONE flag, mean that M0 will start working */ |
| 80 | mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0); |
Derek Basehore | c8e5c78 | 2017-02-24 14:33:03 +0800 | [diff] [blame] | 81 | dmbst(); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 82 | |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 83 | mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, |
| 84 | BITS_WITH_WMASK(0x0, 0x4, 0)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 85 | |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 86 | udelay(5); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 87 | /* start M0 */ |
| 88 | mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 89 | BITS_WITH_WMASK(0x0, 0x20, 0)); |
| 90 | dmbst(); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | void m0_stop(void) |
| 94 | { |
| 95 | /* stop M0 */ |
| 96 | mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, |
| 97 | BITS_WITH_WMASK(0x24, 0x24, 0)); |
| 98 | |
| 99 | /* disable clocks for M0 */ |
| 100 | mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 101 | BITS_WITH_WMASK(0xf, 0xf, 0)); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | void m0_wait_done(void) |
| 105 | { |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 106 | do { |
Derek Basehore | c8e5c78 | 2017-02-24 14:33:03 +0800 | [diff] [blame] | 107 | /* |
| 108 | * Don't starve the M0 for access to SRAM, so delay before |
| 109 | * reading the PARAM_M0_DONE value again. |
| 110 | */ |
| 111 | udelay(5); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 112 | dsb(); |
Lin Huang | b4a7676 | 2016-12-12 15:18:08 +0800 | [diff] [blame] | 113 | } while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG); |
| 114 | |
| 115 | /* |
| 116 | * Let the M0 settle into WFI before we leave. This is so we don't reset |
| 117 | * the M0 in a bad spot which can cause problems with the M0. |
| 118 | */ |
| 119 | udelay(10); |
| 120 | dsb(); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 121 | } |