blob: 71be71d7d4b5c6dba98b755fac3eba084ac7d694 [file] [log] [blame]
Caesar Wangb4003742016-10-12 08:10:12 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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29 */
30
Xing Zhengb4bcc1d2017-02-24 16:26:11 +080031#include <pmu_regs.h>
Xing Zheng93280b72016-10-26 21:25:26 +080032#include "rk3399_mcu.h"
Caesar Wangb4003742016-10-12 08:10:12 +080033
Xing Zheng93280b72016-10-26 21:25:26 +080034#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
35
36#define SCR_SLEEPDEEP_SHIFT (1 << 2)
37
38void handle_suspend(void)
39{
40 unsigned int status_value;
41
42 while (1) {
43 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST);
44 if (status_value) {
45 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01);
46 return;
47 }
Caesar Wangb4003742016-10-12 08:10:12 +080048 }
49
Xing Zheng93280b72016-10-26 21:25:26 +080050 /* m0 enter deep sleep mode */
51 mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT);
Caesar Wangb4003742016-10-12 08:10:12 +080052}