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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl31.h>
35#include <bl_common.h>
36#include <console.h>
37#include <cortex_a57.h>
38#include <cortex_a53.h>
39#include <debug.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053040#include <errno.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053041#include <memctrl.h>
42#include <mmio.h>
43#include <platform.h>
44#include <platform_def.h>
45#include <stddef.h>
46#include <tegra_private.h>
47
48/*******************************************************************************
49 * Declarations of linker defined symbols which will help us find the layout
50 * of trusted SRAM
51 ******************************************************************************/
52extern unsigned long __RO_START__;
53extern unsigned long __RO_END__;
54extern unsigned long __BL31_END__;
55
56#if USE_COHERENT_MEM
57extern unsigned long __COHERENT_RAM_START__;
58extern unsigned long __COHERENT_RAM_END__;
59#endif
60
61extern uint64_t tegra_bl31_phys_base;
62
63/*
64 * The next 3 constants identify the extents of the code, RO data region and the
65 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
66 * therefore they must be page-aligned. It is the responsibility of the linker
67 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
68 * refer to page-aligned addresses.
69 */
70#define BL31_RO_BASE (unsigned long)(&__RO_START__)
71#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
72#define BL31_END (unsigned long)(&__BL31_END__)
73
74#if USE_COHERENT_MEM
75/*
76 * The next 2 constants identify the extents of the coherent memory region.
77 * These addresses are used by the MMU setup code and therefore they must be
78 * page-aligned. It is the responsibility of the linker script to ensure that
79 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
80 * refer to page-aligned addresses.
81 */
82#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
83#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
84#endif
85
Varun Wadekar52a15982015-06-05 12:57:27 +053086static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053087static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +053088 .tzdram_size = (uint64_t)TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053089};
90
91/*******************************************************************************
92 * This variable holds the non-secure image entry address
93 ******************************************************************************/
94extern uint64_t ns_image_entrypoint;
95
96/*******************************************************************************
97 * Return a pointer to the 'entry_point_info' structure of the next image for
98 * security state specified. BL33 corresponds to the non-secure image type
99 * while BL32 corresponds to the secure image type.
100 ******************************************************************************/
101entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
102{
103 if (type == NON_SECURE)
104 return &bl33_image_ep_info;
105
Varun Wadekar52a15982015-06-05 12:57:27 +0530106 if (type == SECURE)
107 return &bl32_image_ep_info;
108
Varun Wadekarb316e242015-05-19 16:48:04 +0530109 return NULL;
110}
111
112/*******************************************************************************
113 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
114 * passes this platform specific information.
115 ******************************************************************************/
116plat_params_from_bl2_t *bl31_get_plat_params(void)
117{
118 return &plat_bl31_params_from_bl2;
119}
120
121/*******************************************************************************
122 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
123 * info.
124 ******************************************************************************/
125void bl31_early_platform_setup(bl31_params_t *from_bl2,
126 void *plat_params_from_bl2)
127{
128 plat_params_from_bl2_t *plat_params =
129 (plat_params_from_bl2_t *)plat_params_from_bl2;
130
131 /*
132 * Configure the UART port to be used as the console
133 */
134 console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
135 TEGRA_CONSOLE_BAUDRATE);
136
137 /* Initialise crash console */
138 plat_crash_console_init();
139
140 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530141 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530142 * They are stored in Secure RAM, in BL2's address space.
143 */
144 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Varun Wadekar52a15982015-06-05 12:57:27 +0530145 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +0530146
147 /*
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +0530148 * Parse platform specific parameters - TZDRAM aperture size
Varun Wadekarb316e242015-05-19 16:48:04 +0530149 */
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +0530150 if (plat_params)
Varun Wadekarb316e242015-05-19 16:48:04 +0530151 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530152}
153
154/*******************************************************************************
155 * Initialize the gic, configure the SCR.
156 ******************************************************************************/
157void bl31_platform_setup(void)
158{
159 uint32_t tmp_reg;
160
161 /*
Varun Wadekarbc74fec2015-07-16 15:47:03 +0530162 * Initialize delay timer
163 */
164 tegra_delay_timer_init();
165
166 /*
Varun Wadekarb316e242015-05-19 16:48:04 +0530167 * Setup secondary CPU POR infrastructure.
168 */
169 plat_secondary_setup();
170
171 /*
172 * Initial Memory Controller configuration.
173 */
174 tegra_memctrl_setup();
175
176 /*
177 * Do initial security configuration to allow DRAM/device access.
178 */
179 tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
180 plat_bl31_params_from_bl2.tzdram_size);
181
182 /* Set the next EL to be AArch64 */
183 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
184 write_scr(tmp_reg);
185
186 /* Initialize the gic cpu and distributor interfaces */
187 tegra_gic_setup();
188}
189
190/*******************************************************************************
191 * Perform the very early platform specific architectural setup here. At the
192 * moment this only intializes the mmu in a quick and dirty way.
193 ******************************************************************************/
194void bl31_plat_arch_setup(void)
195{
196 unsigned long bl31_base_pa = tegra_bl31_phys_base;
197 unsigned long total_base = bl31_base_pa;
Varun Wadekare1eaf8e2015-08-11 14:20:14 +0530198 unsigned long total_size = BL32_BASE - BL31_RO_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530199 unsigned long ro_start = bl31_base_pa;
200 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE;
Varun Wadekarb316e242015-05-19 16:48:04 +0530201 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530202#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530203 unsigned long coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530204#endif
205
206 /* add memory regions */
207 mmap_add_region(total_base, total_base,
208 total_size,
209 MT_MEMORY | MT_RW | MT_SECURE);
210 mmap_add_region(ro_start, ro_start,
211 ro_size,
212 MT_MEMORY | MT_RO | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530213
Varun Wadekarb316e242015-05-19 16:48:04 +0530214#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530215 coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
216 coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
217
Varun Wadekarb316e242015-05-19 16:48:04 +0530218 mmap_add_region(coh_start, coh_start,
219 coh_size,
220 MT_DEVICE | MT_RW | MT_SECURE);
221#endif
222
223 /* add MMIO space */
224 plat_mmio_map = plat_get_mmio_map();
225 if (plat_mmio_map)
226 mmap_add(plat_mmio_map);
227 else
228 WARN("MMIO map not available\n");
229
230 /* set up translation tables */
231 init_xlat_tables();
232
233 /* enable the MMU */
234 enable_mmu_el3(0);
235}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530236
237/*******************************************************************************
238 * Check if the given NS DRAM range is valid
239 ******************************************************************************/
240int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
241{
242 uint64_t end = base + size_in_bytes - 1;
243
244 /*
245 * Check if the NS DRAM address is valid
246 */
247 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
248 (base >= end)) {
249 ERROR("NS address is out-of-bounds!\n");
250 return -EFAULT;
251 }
252
253 /*
254 * TZDRAM aperture contains the BL31 and BL32 images, so we need
255 * to check if the NS DRAM range overlaps the TZDRAM aperture.
256 */
257 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
258 ERROR("NS address overlaps TZDRAM!\n");
259 return -ENOTSUP;
260 }
261
262 /* valid NS address */
263 return 0;
264}