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git01.mediatek.com / filogic / atf / fb10bfdc61dcecbf8b1a19c28ebbe1b5599a8b38 / . / plat / arm / board / rdn1edge / platform.mk
blob: 135676d43b073ade872407e154ef9753b14e0b68 [file] [log] [blame]
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]1#
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]2# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include plat/arm/css/sgi/sgi-common.mk
8
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]9RDN1EDGE_BASE = plat/arm/board/rdn1edge
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]10
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]11PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]12
John Tsichritzis56369c12019-02-19 13:49:06 +0000[diff] [blame]13SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]14
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]15BL1_SOURCES += ${SGI_CPU_SOURCES} \
16 ${RDN1EDGE_BASE}/rdn1edge_err.c
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]17
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]18BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \
19 ${RDN1EDGE_BASE}/rdn1edge_security.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100[diff] [blame]20 ${RDN1EDGE_BASE}/rdn1edge_err.c \
Vijayenthiran Subramaniam22141b62018-10-25 22:20:24 +0530[diff] [blame]21 drivers/arm/tzc/tzc_dmc620.c \
22 lib/utils/mem_region.c \
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]23 plat/arm/common/arm_nor_psci_mem_protect.c
24
25BL31_SOURCES += ${SGI_CPU_SOURCES} \
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]26 ${RDN1EDGE_BASE}/rdn1edge_plat.c \
Vijayenthiran Subramaniamf5cb00f2019-12-27 19:27:57 +0530[diff] [blame]27 ${RDN1EDGE_BASE}/rdn1edge_topology.c \
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]28 drivers/cfi/v2m/v2m_flash.c \
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]29 drivers/arm/gic/v3/gic600_multichip.c \
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]30 lib/utils/mem_region.c \
31 plat/arm/common/arm_nor_psci_mem_protect.c
32
Max Shvetsov06dba292019-12-06 11:50:12 +0000[diff] [blame]33ifeq (${TRUSTED_BOARD_BOOT}, 1)
34BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
35BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
36endif
37
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]38# Enable dynamic addition of MMAP regions in BL31
39BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
40
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]41# Add the FDT_SOURCES and options for Dynamic Config
Louis Mayencourt9fdfae32020-02-12 09:26:09 +0000[diff] [blame]42FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts
43TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]44
45# Add the TB_FW_CONFIG to FIP and specify the same to certtool
46$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
47
Chandni Cherukuri15ec1e52019-02-22 13:41:03 +0530[diff] [blame]48FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
Chandni Cherukuri29ea98d2018-11-28 11:26:19 +0530[diff] [blame]49NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]50
Chandni Cherukuri29ea98d2018-11-28 11:26:19 +0530[diff] [blame]51# Add the NT_FW_CONFIG to FIP and specify the same to certtool
52$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]53
Vijayenthiran Subramaniamcfa3aea2020-02-12 13:26:33 +0530[diff] [blame]54$(eval $(call CREATE_SEQ,SEQ,2))
55ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
56 $(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
Vijayenthiran Subramaniamc4e68a42019-10-28 14:49:48 +0530[diff] [blame]57 set to ${CSS_SGI_CHIP_COUNT}.")
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]58endif
59
Chandni Cherukurif7813232018-09-16 21:06:29 +0530[diff] [blame]60override CTX_INCLUDE_AARCH32_REGS := 0