blob: 34866f06e5de303f13818fbe90f6e6c8f0379c68 [file] [log] [blame]
Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
7#include <assert.h>
8#include <bl_common.h>
9#include <console.h>
10#include <gicv2.h>
11#include <platform_def.h>
12#include "qemu_private.h"
13
14/*
15 * The next 3 constants identify the extents of the code, RO data region and the
16 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
17 * therefore they must be page-aligned. It is the responsibility of the linker
18 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
19 * refer to page-aligned addresses.
20 */
21#define BL31_RO_BASE (unsigned long)(&__RO_START__)
22#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
23#define BL31_END (unsigned long)(&__BL31_END__)
24
25/*
Jens Wiklander52c798e2015-12-07 14:37:10 +010026 * Placeholder variables for copying the arguments that have been passed to
27 * BL3-1 from BL2.
28 */
29static entry_point_info_t bl32_image_ep_info;
30static entry_point_info_t bl33_image_ep_info;
31
32/*******************************************************************************
33 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
34 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
35 * they are lost (potentially). This needs to be done before the MMU is
36 * initialized so that the memory layout can be used while creating page
37 * tables. BL2 has flushed this information to memory, so we are guaranteed
38 * to pick up good data.
39 ******************************************************************************/
40void bl31_early_platform_setup(bl31_params_t *from_bl2,
41 void *plat_params_from_bl2)
42{
43 /* Initialize the console to provide early debug support */
44 console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
45 PLAT_QEMU_CONSOLE_BAUDRATE);
46
47 /*
48 * Check params passed from BL2 should not be NULL,
49 */
50 assert(from_bl2 != NULL);
51 assert(from_bl2->h.type == PARAM_BL31);
52 assert(from_bl2->h.version >= VERSION_1);
53 /*
54 * In debug builds, we pass a special value in 'plat_params_from_bl2'
55 * to verify platform parameters from BL2 to BL3-1.
56 * In release builds, it's not used.
57 */
58 assert(((unsigned long long)plat_params_from_bl2) ==
59 QEMU_BL31_PLAT_PARAM_VAL);
60
61 /*
62 * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information.
63 * They are stored in Secure RAM, in BL2's address space.
64 */
65 if (from_bl2->bl32_ep_info)
66 bl32_image_ep_info = *from_bl2->bl32_ep_info;
67 bl33_image_ep_info = *from_bl2->bl33_ep_info;
68}
69
70void bl31_plat_arch_setup(void)
71{
72 qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
73 BL31_RO_BASE, BL31_RO_LIMIT,
Masahiro Yamada0fac5af2016-12-28 16:11:41 +090074 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
Jens Wiklander52c798e2015-12-07 14:37:10 +010075}
76
77static const unsigned int irq_sec_array[] = {
78 QEMU_IRQ_SEC_SGI_0,
79 QEMU_IRQ_SEC_SGI_1,
80 QEMU_IRQ_SEC_SGI_2,
81 QEMU_IRQ_SEC_SGI_3,
82 QEMU_IRQ_SEC_SGI_4,
83 QEMU_IRQ_SEC_SGI_5,
84 QEMU_IRQ_SEC_SGI_6,
85 QEMU_IRQ_SEC_SGI_7,
86};
87
88static const struct gicv2_driver_data plat_gicv2_driver_data = {
89 .gicd_base = GICD_BASE,
90 .gicc_base = GICC_BASE,
91 .g0_interrupt_num = ARRAY_SIZE(irq_sec_array),
92 .g0_interrupt_array = irq_sec_array,
93};
94
95void bl31_platform_setup(void)
96{
97 /* Initialize the gic cpu and distributor interfaces */
98 gicv2_driver_init(&plat_gicv2_driver_data);
99 gicv2_distif_init();
100 gicv2_pcpu_distif_init();
101 gicv2_cpuif_enable();
102}
103
104unsigned int plat_get_syscnt_freq2(void)
105{
106 return SYS_COUNTER_FREQ_IN_TICKS;
107}
108
109/*******************************************************************************
110 * Return a pointer to the 'entry_point_info' structure of the next image
111 * for the security state specified. BL3-3 corresponds to the non-secure
112 * image type while BL3-2 corresponds to the secure image type. A NULL
113 * pointer is returned if the image does not exist.
114 ******************************************************************************/
115entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
116{
117 entry_point_info_t *next_image_info;
118
119 assert(sec_state_is_valid(type));
120 next_image_info = (type == NON_SECURE)
121 ? &bl33_image_ep_info : &bl32_image_ep_info;
122 /*
123 * None of the images on the ARM development platforms can have 0x0
124 * as the entrypoint
125 */
126 if (next_image_info->pc)
127 return next_image_info;
128 else
129 return NULL;
130}