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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri72084192016-02-08 16:29:30 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <cpu_macros.S>
9#include <css_def.h>
10
11 .weak plat_secondary_cold_boot_setup
Soby Mathewfec4eb72015-07-01 16:16:20 +010012 .weak plat_get_my_entrypoint
David Wang323ebe82015-10-22 13:30:50 +080013 .globl css_calc_core_pos_swap_cluster
Soby Mathewfec4eb72015-07-01 16:16:20 +010014 .weak plat_is_my_cpu_primary
Dan Handley9df48042015-03-19 18:58:55 +000015
Sandrine Bailleux4c79d202015-04-29 16:28:52 +010016 /* ---------------------------------------------------------------------
17 * void plat_secondary_cold_boot_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +000018 *
Sandrine Bailleux4c79d202015-04-29 16:28:52 +010019 * In the normal boot flow, cold-booting secondary CPUs is not yet
20 * implemented and they panic.
21 *
22 * When booting an EL3 payload, secondary CPUs are placed in a holding
23 * pen, waiting for their mailbox to be populated. Note that all CPUs
24 * share the same mailbox ; therefore, populating it will release all
25 * CPUs from their holding pen. If finer-grained control is needed then
26 * this should be handled in the code that secondary CPUs jump to.
27 * ---------------------------------------------------------------------
Dan Handley9df48042015-03-19 18:58:55 +000028 */
29func plat_secondary_cold_boot_setup
Sandrine Bailleux4c79d202015-04-29 16:28:52 +010030#ifndef EL3_PAYLOAD_BASE
31 /* TODO: Implement secondary CPU cold boot setup on CSS platforms */
Dan Handley9df48042015-03-19 18:58:55 +000032cb_panic:
33 b cb_panic
Sandrine Bailleux4c79d202015-04-29 16:28:52 +010034#else
35 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
36
37 /* Wait until the mailbox gets populated */
38poll_mailbox:
39 ldr x1, [x0]
40 cbz x1, 1f
41 br x1
421:
43 wfe
44 b poll_mailbox
45#endif /* EL3_PAYLOAD_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000046endfunc plat_secondary_cold_boot_setup
47
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +010048 /* ---------------------------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +010049 * uintptr_t plat_get_my_entrypoint (void);
Dan Handley9df48042015-03-19 18:58:55 +000050 *
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +010051 * Main job of this routine is to distinguish between a cold and a warm
52 * boot. On CSS platforms, this distinction is based on the contents of
53 * the Trusted Mailbox. It is initialised to zero by the SCP before the
54 * AP cores are released from reset. Therefore, a zero mailbox means
55 * it's a cold reset.
Dan Handley9df48042015-03-19 18:58:55 +000056 *
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +010057 * This functions returns the contents of the mailbox, i.e.:
58 * - 0 for a cold boot;
59 * - the warm boot entrypoint for a warm boot.
60 * ---------------------------------------------------------------------
Dan Handley9df48042015-03-19 18:58:55 +000061 */
Soby Mathewfec4eb72015-07-01 16:16:20 +010062func plat_get_my_entrypoint
Soby Mathewfeac8fc2015-09-29 15:47:16 +010063 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +010064 ldr x0, [x0]
65 ret
Soby Mathewfec4eb72015-07-01 16:16:20 +010066endfunc plat_get_my_entrypoint
Dan Handley9df48042015-03-19 18:58:55 +000067
Soby Mathewfec4eb72015-07-01 16:16:20 +010068 /* -----------------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +010069 * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
David Wang323ebe82015-10-22 13:30:50 +080070 * Utility function to calculate the core position by
Soby Mathewfec4eb72015-07-01 16:16:20 +010071 * swapping the cluster order. This is necessary in order to
72 * match the format of the boot information passed by the SCP
Soby Matheweb3bbf12015-06-08 12:32:50 +010073 * and read in plat_is_my_cpu_primary below.
Soby Mathewfec4eb72015-07-01 16:16:20 +010074 * -----------------------------------------------------------
Dan Handley9df48042015-03-19 18:58:55 +000075 */
David Wang323ebe82015-10-22 13:30:50 +080076func css_calc_core_pos_swap_cluster
Dan Handley9df48042015-03-19 18:58:55 +000077 and x1, x0, #MPIDR_CPU_MASK
78 and x0, x0, #MPIDR_CLUSTER_MASK
79 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
80 add x0, x1, x0, LSR #6
81 ret
David Wang323ebe82015-10-22 13:30:50 +080082endfunc css_calc_core_pos_swap_cluster
Dan Handley9df48042015-03-19 18:58:55 +000083
84 /* -----------------------------------------------------
Soby Mathewfec4eb72015-07-01 16:16:20 +010085 * unsigned int plat_is_my_cpu_primary (void);
Dan Handley9df48042015-03-19 18:58:55 +000086 *
Soby Mathewfec4eb72015-07-01 16:16:20 +010087 * Find out whether the current cpu is the primary
Dan Handley9df48042015-03-19 18:58:55 +000088 * cpu (applicable ony after a cold boot)
89 * -----------------------------------------------------
90 */
Soby Mathewfec4eb72015-07-01 16:16:20 +010091func plat_is_my_cpu_primary
Dan Handley9df48042015-03-19 18:58:55 +000092 mov x9, x30
Soby Mathewfec4eb72015-07-01 16:16:20 +010093 bl plat_my_core_pos
Dan Handley9df48042015-03-19 18:58:55 +000094 ldr x1, =SCP_BOOT_CFG_ADDR
95 ldr x1, [x1]
Vikram Kanigiri72084192016-02-08 16:29:30 +000096 ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
97 #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
Dan Handley9df48042015-03-19 18:58:55 +000098 cmp x0, x1
Soby Matheweb3bbf12015-06-08 12:32:50 +010099 cset w0, eq
Dan Handley9df48042015-03-19 18:58:55 +0000100 ret x9
Soby Mathewfec4eb72015-07-01 16:16:20 +0100101endfunc plat_is_my_cpu_primary