Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame^] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __XLAT_TABLES_ARCH_H__ |
| 8 | #define __XLAT_TABLES_ARCH_H__ |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <platform_def.h> |
| 12 | #include <xlat_tables_defs.h> |
| 13 | |
| 14 | /* |
| 15 | * In AArch32 state, the MMU only supports 4KB page granularity, which means |
| 16 | * that the first translation table level is either 1 or 2. Both of them are |
| 17 | * allowed to have block and table descriptors. See section G4.5.6 of the |
| 18 | * ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information. |
| 19 | * |
| 20 | * The define below specifies the first table level that allows block |
| 21 | * descriptors. |
| 22 | */ |
| 23 | |
| 24 | #define MIN_LVL_BLOCK_DESC 1 |
| 25 | |
| 26 | /* |
| 27 | * Each platform can define the size of the virtual address space, which is |
| 28 | * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus |
| 29 | * the width of said address space. The value of TTBCR.TxSZ must be in the |
| 30 | * range 0 to 7 [1], which means that the virtual address space width must be |
| 31 | * in the range 32 to 25 bits. |
| 32 | * |
| 33 | * Here we calculate the initial lookup level from the value of |
| 34 | * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual |
| 35 | * address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or |
| 36 | * narrower address spaces are not supported. As a result, level 3 cannot be |
| 37 | * used as initial lookup level with 4 KB granularity [1]. |
| 38 | * |
| 39 | * For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE == |
| 40 | * 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table |
| 41 | * G4-5 in the ARM ARM, the initial lookup level for an address space like that |
| 42 | * is 1. |
| 43 | * |
| 44 | * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more |
| 45 | * information: |
| 46 | * [1] Section G4.6.5 |
| 47 | */ |
| 48 | |
| 49 | #if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN)) |
| 50 | |
| 51 | # error "PLAT_VIRT_ADDR_SPACE_SIZE is too big." |
| 52 | |
| 53 | #elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) |
| 54 | |
| 55 | # define XLAT_TABLE_LEVEL_BASE 1 |
| 56 | # define NUM_BASE_LEVEL_ENTRIES \ |
| 57 | (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) |
| 58 | |
| 59 | #elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX)) |
| 60 | |
| 61 | # define XLAT_TABLE_LEVEL_BASE 2 |
| 62 | # define NUM_BASE_LEVEL_ENTRIES \ |
| 63 | (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) |
| 64 | |
| 65 | #else |
| 66 | |
| 67 | # error "PLAT_VIRT_ADDR_SPACE_SIZE is too small." |
| 68 | |
| 69 | #endif |
| 70 | |
| 71 | #endif /* __XLAT_TABLES_ARCH_H__ */ |