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Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __XLAT_TABLES_DEFS_H__
32#define __XLAT_TABLES_DEFS_H__
33
Scott Brandenbf404c02017-04-10 11:45:52 -070034#include <utils_def.h>
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000035
36/* Miscellaneous MMU related constants */
37#define NUM_2MB_IN_GB (1 << 9)
38#define NUM_4K_IN_2MB (1 << 9)
39#define NUM_GB_IN_4GB (1 << 2)
40
41#define TWO_MB_SHIFT 21
42#define ONE_GB_SHIFT 30
43#define FOUR_KB_SHIFT 12
44
45#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
46#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
47#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
48
49#define INVALID_DESC 0x0
50#define BLOCK_DESC 0x1 /* Table levels 0-2 */
51#define TABLE_DESC 0x3 /* Table levels 0-2 */
52#define PAGE_DESC 0x3 /* Table level 3 */
53#define DESC_MASK 0x3
54
55#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
56#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
57#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
58
59#define XN (ULL(1) << 2)
60#define PXN (ULL(1) << 1)
61#define CONT_HINT (ULL(1) << 0)
62#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
63
64#define NON_GLOBAL (1 << 9)
65#define ACCESS_FLAG (1 << 8)
66#define NSH (0x0 << 6)
67#define OSH (0x2 << 6)
68#define ISH (0x3 << 6)
69
70#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
71
72#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */
73#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
74#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
75#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
76
77#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
78#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
79
80#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
81#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
82
83#ifdef AARCH32
84#define XLAT_TABLE_LEVEL_MIN 1
85#else
86#define XLAT_TABLE_LEVEL_MIN 0
87#endif /* AARCH32 */
88
89#define XLAT_TABLE_LEVEL_MAX 3
90
91/* Values for number of entries in each MMU translation table */
92#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
93#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
94#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
95
96/* Values to convert a memory address to an index into a translation table */
97#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
98#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
99#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
100#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
101#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
102 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
103
104#define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
105/* Mask to get the bits used to index inside a block of a certain level */
106#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1)
107/* Mask to get the address bits common to a block of a certain table level*/
108#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
109
110/*
111 * AP[1] bit is ignored by hardware and is
112 * treated as if it is One in EL2/EL3
113 */
114#define AP_RO (0x1 << 5)
115#define AP_RW (0x0 << 5)
116
117#define NS (0x1 << 3)
118#define ATTR_NON_CACHEABLE_INDEX 0x2
119#define ATTR_DEVICE_INDEX 0x1
120#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
121#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
122/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
123#define ATTR_NON_CACHEABLE (0x44)
124/* Device-nGnRE */
125#define ATTR_DEVICE (0x4)
126/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
127#define ATTR_IWBWA_OWBWA_NTR (0xff)
128#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
129#define ATTR_INDEX_MASK 0x3
130#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
131
132/*
133 * Flags to override default values used to program system registers while
134 * enabling the MMU.
135 */
136#define DISABLE_DCACHE (1 << 0)
137
Summer Qindaf5dbb2017-03-16 17:16:34 +0000138/*
139 * This flag marks the translation tables are Non-cacheable for MMU accesses.
140 * If the flag is not specified, by default the tables are cacheable.
141 */
142#define XLAT_TABLE_NC (1 << 1)
143
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000144#endif /* __XLAT_TABLES_DEFS_H__ */